Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer

This commit is contained in:
Florent Kermarrec 2019-11-16 14:39:18 +01:00
parent 9642893371
commit 6059712794
2 changed files with 11 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
litex/soc/interconnect/packet.py
View File

@ -238,7 +238,7 @@ class Packetizer(Module):
) )
) )
header_offset_multiplier = 1 if header_words == 1 else 2 header_offset_multiplier = 1 if header_words == 1 else 2
self.sync += If(sink.ready, sink_d.eq(sink)) self.sync += If(source.ready, sink_d.eq(sink))
fsm.act("UNALIGNED-DATA-COPY", fsm.act("UNALIGNED-DATA-COPY",
source.valid.eq(sink.valid | sink_d.last), source.valid.eq(sink.valid | sink_d.last),
source.last.eq(sink_d.last), source.last.eq(sink_d.last),
@ -249,7 +249,7 @@ class Packetizer(Module):
), ),
source.data[header_leftover*8:].eq(sink.data), source.data[header_leftover*8:].eq(sink.data),
If(source.valid & source.ready, If(source.valid & source.ready,
sink.ready.eq(1), sink.ready.eq(~source.last),
NextValue(fsm_from_idle, 0), NextValue(fsm_from_idle, 0),
If(source.last, If(source.last,
NextState("IDLE") NextState("IDLE")
@ -339,11 +339,11 @@ class Depacketizer(Module):
) )
) )
) )
self.sync += If(sink.valid & sink.ready, sink_d.eq(sink)) self.sync += If(sink.ready, sink_d.eq(sink))
fsm.act("UNALIGNED-DATA-COPY", fsm.act("UNALIGNED-DATA-COPY",
source.valid.eq((sink.valid & ~fsm_from_idle) | no_payload), source.valid.eq((sink.valid & ~fsm_from_idle) | no_payload),
source.last.eq(sink.last | no_payload), source.last.eq(sink.last | no_payload),
sink.ready.eq(source.ready), sink.ready.eq(source.ready | fsm_from_idle),
If(sink.valid & sink.ready, If(sink.valid & sink.ready,
NextValue(fsm_from_idle, 0), NextValue(fsm_from_idle, 0),
If(fsm_from_idle, If(fsm_from_idle,

10
test/test_packet.py
View File

@ -74,16 +74,21 @@ class TestPacket(unittest.TestCase):
while prng.randrange(100) < valid_rand: while prng.randrange(100) < valid_rand:
yield yield
def checker(dut): def checker(dut, ready_rand=50):
dut.header_errors = 0 dut.header_errors = 0
dut.data_errors = 0 dut.data_errors = 0
dut.last_errors = 0 dut.last_errors = 0
# Receive and check packets # Receive and check packets
yield dut.source.ready.eq(1)
for packet in packets: for packet in packets:
for n, data in enumerate(packet.datas): for n, data in enumerate(packet.datas):
yield dut.source.ready.eq(0)
yield
while (yield dut.source.valid) == 0: while (yield dut.source.valid) == 0:
yield yield
while prng.randrange(100) < ready_rand:
yield
yield dut.source.ready.eq(1)
yield
for field in ["field_8b", "field_16b", "field_32b", "field_64b", "field_128b"]: for field in ["field_8b", "field_16b", "field_32b", "field_64b", "field_128b"]:
if (yield getattr(dut.source, field)) != packet.header[field]: if (yield getattr(dut.source, field)) != packet.header[field]:
dut.header_errors += 1 dut.header_errors += 1
@ -92,7 +97,6 @@ class TestPacket(unittest.TestCase):
dut.data_errors += 1 dut.data_errors += 1
if ((yield dut.source.last) != (n == (len(packet.datas) - 1))): if ((yield dut.source.last) != (n == (len(packet.datas) - 1))):
dut.last_errors += 1 dut.last_errors += 1
yield
yield yield
class DUT(Module): class DUT(Module):