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cores/clock/xilinx_us: Remove USP modules (refactoring issue).

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Florent Kermarrec 2021-03-04 14:42:03 +01:00
parent 2d5b4b206b
commit 60e2d3335f
1 changed files with 0 additions and 87 deletions
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87
litex/soc/cores/clock/xilinx_us.py
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@ -125,90 +125,3 @@ class USIDELAYCTRL(Module):
o_RDY = ic_ready),
AsyncResetSynchronizer(self.cd_ic, ic_reset)
]
# Xilinx / Ultrascale Plus -------------------------------------------------------------------------
# TODO:
# - use Ultrascale Plus primitives instead of 7-Series' ones. (Vivado recognize and convert them).
class USPPLL(XilinxClocking):
nclkouts_max = 6
def __init__(self, speedgrade=-1):
self.logger = logging.getLogger("USPPLL")
self.logger.info("Creating USPPLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
XilinxClocking.__init__(self)
self.divclk_divide_range = (1, 56+1)
self.clkin_freq_range = {
-1: (70e6, 800e6),
-2: (70e6, 933e6),
-3: (70e6, 1066e6),
}[speedgrade]
self.vco_freq_range = {
-1: (750e6, 1500e6),
-2: (750e6, 1500e6),
-3: (750e6, 1500e6),
}[speedgrade]
def do_finalize(self):
XilinxClocking.do_finalize(self)
config = self.compute_config()
pll_fb = Signal()
self.params.update(
p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset,
# VCO
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
)
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
self.params["o_CLKOUT{}".format(n)] = clk
self.specials += Instance("PLLE2_ADV", **self.params)
class USPMMCM(XilinxClocking):
nclkouts_max = 7
def __init__(self, speedgrade=-1):
self.logger = logging.getLogger("USPMMCM")
self.logger.info("Creating USPMMCM, {}.".format(colorer("speedgrade {}".format(speedgrade))))
XilinxClocking.__init__(self)
self.divclk_divide_range = (1, 106+1)
self.clkin_freq_range = {
-1: (10e6, 800e6),
-2: (10e6, 933e6),
-3: (10e6, 1066e6),
}[speedgrade]
self.vco_freq_range = {
-1: (800e6, 1600e6),
-2: (800e6, 1600e6),
-3: (800e6, 1600e6),
}[speedgrade]
def do_finalize(self):
XilinxClocking.do_finalize(self)
config = self.compute_config()
mmcm_fb = Signal()
self.params.update(
p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset,
# VCO
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
)
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
if n == 0:
self.params["p_CLKOUT{}_DIVIDE_F".format(n)] = config["clkout{}_divide".format(n)]
else:
self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
self.params["o_CLKOUT{}".format(n)] = clk
self.specials += Instance("MMCME2_ADV", **self.params)
class USPIDELAYCTRL(USIDELAYCTRL): pass