cpu/cva6: Switch to common PLIC handling code to make it similar to other PLIC based CPU and avoid code "duplication".
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@ -90,6 +90,7 @@ class CVA6(CPU):
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def gcc_flags(self):
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def gcc_flags(self):
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flags = GCC_FLAGS[self.variant]
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flags = GCC_FLAGS[self.variant]
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flags += "-D__cva6__ "
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flags += "-D__cva6__ "
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flags += "-D__riscv_plic__ "
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#flags += f" -DUART_POLLING"
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#flags += f" -DUART_POLLING"
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return flags
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return flags
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@ -9,15 +9,16 @@ extern "C" {
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#include <generated/csr.h>
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#include <generated/csr.h>
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#include <generated/soc.h>
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#include <generated/soc.h>
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#define PLIC_SOURCE_0 0x0c000004L // source 0 priority
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// The CVA6 uses a Platform-Level Interrupt Controller (PLIC) which
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#define PLIC_SOURCE_1 0x0c000008L // source 1 priority
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// is programmed and queried via a set of MMIO registers.
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#define PLIC_PENDING 0x0c001000L // start of pending array
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#define PLIC_M_ENABLE 0x0c002000L // Start of Hart 0 M-mode enables
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#define PLIC_BASE 0x0c000000L // Base address and per-pin priority array
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#define PLIC_S_ENABLE 0x0c002100L // Start of Hart 0 S-mode enables
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#define PLIC_PENDING 0x0c001000L // Bit field matching currently pending pins
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#define PLIC_M_THRESHOLD 0x0c200000L // hart 0 M-mode priority threshold
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#define PLIC_ENABLED 0x0c002000L // Bit field corresponding to the current mask
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#define PLIC_M_CLAIM 0x0c200004L // hart 0 M-mode priority claim/complete
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#define PLIC_THRSHLD 0x0c200000L // Per-pin priority must be >= this to trigger
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#define PLIC_S_THRESHOLD 0x0c200100L // hart 0 S-mode priority threshold
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#define PLIC_CLAIM 0x0c200004L // Claim & completion register address
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#define PLIC_S_CLAIM 0x0c200104L // hart 0 S-mode priority claim/complete
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#define PLIC_EXT_IRQ_BASE 1
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static inline unsigned int irq_getie(void)
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static inline unsigned int irq_getie(void)
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{
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{
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@ -31,12 +32,12 @@ static inline void irq_setie(unsigned int ie)
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static inline unsigned int irq_getmask(void)
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static inline unsigned int irq_getmask(void)
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{
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{
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return *((unsigned int *)PLIC_M_ENABLE) >> 1;
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return *((unsigned int *)PLIC_ENABLED) >> 1;
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}
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}
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static inline void irq_setmask(unsigned int mask)
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static inline void irq_setmask(unsigned int mask)
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{
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{
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*((unsigned int *)PLIC_M_ENABLE) = mask << 1;
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*((unsigned int *)PLIC_ENABLED) = mask << 1;
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}
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}
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static inline unsigned int irq_pending(void)
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static inline unsigned int irq_pending(void)
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@ -153,47 +153,8 @@ void isr_dec(void)
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mtdec(0x000000000ffffff);
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mtdec(0x000000000ffffff);
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}
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}
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#elif defined(__cva6__)
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void plic_init(void);
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void plic_init(void)
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{
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int i;
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// priorities for interrupt pins 0...7
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for (i = 0; i < 8; i++)
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*((unsigned int *)PLIC_SOURCE_0 + i) = 1;
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// enable interrupt pins 0...7 (M-mode)
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*((unsigned int *)PLIC_M_ENABLE) = 0xff;
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// set priority threshold to 0 (any priority > 0 triggers interrupt)
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*((unsigned int *)PLIC_M_THRESHOLD) = 0;
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}
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void isr(void)
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{
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unsigned int claim;
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while ((claim = *((unsigned int *)PLIC_M_CLAIM))) {
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switch (claim - 1) {
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case UART_INTERRUPT:
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uart_isr();
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break;
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default:
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printf("## PLIC: Unhandled claim: %d\n", claim);
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printf("# plic_enabled: %08x\n", irq_getmask());
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printf("# plic_pending: %08x\n", irq_pending());
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printf("# mepc: %016lx\n", csrr(mepc));
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printf("# mcause: %016lx\n", csrr(mcause));
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printf("# mtval: %016lx\n", csrr(mtval));
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printf("# mie: %016lx\n", csrr(mie));
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printf("# mip: %016lx\n", csrr(mip));
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printf("###########################\n\n");
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break;
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}
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*((unsigned int *)PLIC_M_CLAIM) = claim;
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}
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}
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#else
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#else
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struct irq_table
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struct irq_table
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{
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{
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isr_t isr;
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isr_t isr;
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