interconnect/stream: add multiplexer and demultiplexer
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@ -113,3 +113,32 @@ class SyncFIFO(_FIFOWrapper):
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class AsyncFIFO(_FIFOWrapper):
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class AsyncFIFO(_FIFOWrapper):
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def __init__(self, layout, depth):
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def __init__(self, layout, depth):
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_FIFOWrapper.__init__(self, fifo.AsyncFIFO, layout, depth)
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_FIFOWrapper.__init__(self, fifo.AsyncFIFO, layout, depth)
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class Multiplexer(Module):
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def __init__(self, layout, n):
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self.source = Source(layout)
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sinks = []
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for i in range(n):
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sink = Sink(layout)
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setattr(self, "sink"+str(i), sink)
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sinks.append(sink)
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self.sel = Signal(max=n)
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# # #
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cases = {}
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for i, sink in enumerate(sinks):
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cases[i] = Record.connect(sink, self.source)
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self.comb += Case(self.sel, cases)
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class Demultiplexer(Module):
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def __init__(self, layout, n):
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self.sink = Sink(layout)
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sources = []
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for i in range(n):
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source = Source(layout)
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setattr(self, "source"+str(i), source)
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sources.append(source)
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self.sel = Signal(max=n)
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