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fix synthesis translate on/off switch

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Nina Engelhardt 2013-07-26 15:48:25 +02:00 committed by Sebastien Bourdeauducq
parent 9c7ad6b05b
commit 61b8958953
1 changed files with 2 additions and 2 deletions
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4
migen/fhdl/verilog.py
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@ -169,8 +169,8 @@ def _printcomb(f, ns, display_run):
if f.comb:
# Generate a dummy event to get the simulator
# to run the combinatorial process once at the beginning.
syn_off = "// synthesis translate off\n"
syn_on = "// synthesis translate on\n"
syn_off = "// synthesis translate_off\n"
syn_on = "// synthesis translate_on\n"
dummy_s = Signal(name_override="dummy_s")
r += syn_off
r += "reg " + _printsig(ns, dummy_s) + ";\n"