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litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl

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Jędrzej Boczar 2021-01-29 11:31:40 +01:00
parent 7abfbd9825
commit 61e605da92
1 changed files with 2 additions and 2 deletions
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4
litex/tools/litex_sim.py
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@ -114,7 +114,7 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq):
elif memtype in ["DDR2", "DDR3"]: elif memtype in ["DDR2", "DDR3"]:
# Settings from s7ddrphy # Settings from s7ddrphy
tck = 2/(2*nphases*clk_freq) tck = 2/(2*nphases*clk_freq)
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_default_cl_cwl(memtype, tck)
cl_sys_latency = get_sys_latency(nphases, cl) cl_sys_latency = get_sys_latency(nphases, cl)
cwl_sys_latency = get_sys_latency(nphases, cwl) cwl_sys_latency = get_sys_latency(nphases, cwl)
rdphase = get_sys_phase(nphases, cl_sys_latency, cl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl)
@ -124,7 +124,7 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq):
elif memtype == "DDR4": elif memtype == "DDR4":
# Settings from usddrphy # Settings from usddrphy
tck = 2/(2*nphases*clk_freq) tck = 2/(2*nphases*clk_freq)
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_default_cl_cwl(memtype, tck)
cl_sys_latency = get_sys_latency(nphases, cl) cl_sys_latency = get_sys_latency(nphases, cl)
cwl_sys_latency = get_sys_latency(nphases, cwl) cwl_sys_latency = get_sys_latency(nphases, cwl)
rdphase = get_sys_phase(nphases, cl_sys_latency, cl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl)