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test/test_wishbone: Add Remapper unit-test for word addressing mode.

This commit is contained in:
Florent Kermarrec 2024-02-21 11:05:35 +01:00
parent c0517cd1cf
commit 6213fd2151
1 changed files with 88 additions and 9 deletions
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97
test/test_wishbone.py
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@ -122,7 +122,7 @@ class TestWishbone(unittest.TestCase):
dut = DUT() dut = DUT()
run_simulation(dut, generator(dut)) run_simulation(dut, generator(dut))
def test_origin_remap(self): def test_origin_remap_byte(self):
def generator(dut): def generator(dut):
yield from dut.master.write(0x0000_0000, 0) yield from dut.master.write(0x0000_0000, 0)
yield from dut.master.write(0x0000_0004, 0) yield from dut.master.write(0x0000_0004, 0)
@ -152,7 +152,6 @@ class TestWishbone(unittest.TestCase):
self.assertEqual((yield dut.slave.adr), 0x0001_0008) self.assertEqual((yield dut.slave.adr), 0x0001_0008)
yield yield
self.assertEqual((yield dut.slave.adr), 0x0001_000c) self.assertEqual((yield dut.slave.adr), 0x0001_000c)
print((yield dut.slave.adr))
class DUT(LiteXModule): class DUT(LiteXModule):
def __init__(self): def __init__(self):
@ -165,7 +164,49 @@ class TestWishbone(unittest.TestCase):
dut = DUT() dut = DUT()
run_simulation(dut, [generator(dut), checker(dut)]) run_simulation(dut, [generator(dut), checker(dut)])
def test_region_remap(self): def test_origin_remap_word(self):
def generator(dut):
yield from dut.master.write(0x0000_0000//4, 0)
yield from dut.master.write(0x0000_0004//4, 0)
yield from dut.master.write(0x0000_0008//4, 0)
yield from dut.master.write(0x0000_000c//4, 0)
yield from dut.master.write(0x1000_0000//4, 0)
yield from dut.master.write(0x1000_0004//4, 0)
yield from dut.master.write(0x1000_0008//4, 0)
yield from dut.master.write(0x1000_000c//4, 0)
def checker(dut):
yield dut.slave.ack.eq(1)
while (yield dut.slave.stb) == 0:
yield
self.assertEqual((yield dut.slave.adr), 0x0001_0000//4)
yield
self.assertEqual((yield dut.slave.adr), 0x0001_0004//4)
yield
self.assertEqual((yield dut.slave.adr), 0x0001_0008//4)
yield
self.assertEqual((yield dut.slave.adr), 0x0001_000c//4)
yield
self.assertEqual((yield dut.slave.adr), 0x0001_0000//4)
yield
self.assertEqual((yield dut.slave.adr), 0x0001_0004//4)
yield
self.assertEqual((yield dut.slave.adr), 0x0001_0008//4)
yield
self.assertEqual((yield dut.slave.adr), 0x0001_000c//4)
class DUT(LiteXModule):
def __init__(self):
self.master = wishbone.Interface(data_width=32, address_width=32, addressing="word")
self.slave = wishbone.Interface(data_width=32, address_width=32, addressing="word")
self.remapper = wishbone.Remapper(self.master, self.slave,
origin = 0x0001_0000,
size = 0x1000_0000,
)
dut = DUT()
run_simulation(dut, [generator(dut), checker(dut)])
def test_region_remap_byte(self):
def generator(dut): def generator(dut):
yield from dut.master.write(0x0000_0000, 0) yield from dut.master.write(0x0000_0000, 0)
yield from dut.master.write(0x0001_0004, 0) yield from dut.master.write(0x0001_0004, 0)
@ -204,15 +245,53 @@ class TestWishbone(unittest.TestCase):
] ]
) )
dut = DUT() dut = DUT()
run_simulation(dut, [generator(dut), checker(dut)], vcd_name="sim.vcd") run_simulation(dut, [generator(dut), checker(dut)])
def test_origin_region_remap(self): def test_region_remap_word(self):
def generator(dut):
yield from dut.master.write(0x0000_0000//4, 0)
yield from dut.master.write(0x0001_0004//4, 0)
yield from dut.master.write(0x0002_0008//4, 0)
yield from dut.master.write(0x0003_000c//4, 0)
def checker(dut):
yield dut.slave.ack.eq(1)
while (yield dut.slave.stb) == 0:
yield
self.assertEqual((yield dut.slave.adr), 0x0000_0000//4)
yield
self.assertEqual((yield dut.slave.adr), 0x1000_0004//4)
yield
self.assertEqual((yield dut.slave.adr), 0x2000_0008//4)
yield
self.assertEqual((yield dut.slave.adr), 0x3000_000c//4)
yield
class DUT(LiteXModule):
def __init__(self):
self.master = wishbone.Interface(data_width=32, address_width=32, addressing="word")
self.slave = wishbone.Interface(data_width=32, address_width=32, addressing="word")
self.remapper = wishbone.Remapper(self.master, self.slave,
src_regions = [
SoCRegion(origin=0x0000_0000, size=0x1000),
SoCRegion(origin=0x0001_0000, size=0x1000),
SoCRegion(origin=0x0002_0000, size=0x1000),
SoCRegion(origin=0x0003_0000, size=0x1000),
],
dst_regions = [
SoCRegion(origin=0x0000_0000, size=0x1000),
SoCRegion(origin=0x1000_0000, size=0x1000),
SoCRegion(origin=0x2000_0000, size=0x1000),
SoCRegion(origin=0x3000_0000, size=0x1000),
]
)
dut = DUT()
run_simulation(dut, [generator(dut), checker(dut)])
def test_origin_region_remap_byte(self):
def generator(dut): def generator(dut):
yield from dut.master.write(0x0000_0000, 0) yield from dut.master.write(0x0000_0000, 0)
yield from dut.master.write(0x0002_0000, 0) yield from dut.master.write(0x0002_0000, 0)
#yield from dut.master.write(0x0001_0004, 0)
#yield from dut.master.write(0x0002_0008, 0)
#yield from dut.master.write(0x0003_000c, 0)
def checker(dut): def checker(dut):
yield dut.slave.ack.eq(1) yield dut.slave.ack.eq(1)
@ -240,4 +319,4 @@ class TestWishbone(unittest.TestCase):
] ]
) )
dut = DUT() dut = DUT()
run_simulation(dut, [generator(dut), checker(dut)], vcd_name="sim.vcd") run_simulation(dut, [generator(dut), checker(dut)])