soc/integration/soc_core: avoid removing uart interrupts (break some designs)

2017-12-30 18:41:49 +01:00 · 2017-12-30 18:41:49 +01:00 · 621aaf6988
parent 377af99678
commit 621aaf6988
1 changed files with 2 additions and 2 deletions
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@ -145,8 +145,8 @@ class SoCCore(Module):
            else:
                self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
                self.submodules.uart = uart.UART(self.uart_phy)
-        else:
-            del self.soc_interrupt_map["uart"]
+        #else:
+        #    del self.soc_interrupt_map["uart"]

        if ident:
            if ident_version: