soc/integration/soc_core: avoid removing uart interrupts (break some designs)
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@ -145,8 +145,8 @@ class SoCCore(Module):
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else:
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else:
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self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
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self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
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self.submodules.uart = uart.UART(self.uart_phy)
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self.submodules.uart = uart.UART(self.uart_phy)
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else:
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#else:
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del self.soc_interrupt_map["uart"]
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# del self.soc_interrupt_map["uart"]
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if ident:
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if ident:
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if ident_version:
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if ident_version:
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