Merge pull request #2145 from trabucayre/litex_vhd2vconvert_instance
build/vhd2v_converter: allows using an instance instead of entity_name + params
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commit
6228d2b024
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@ -37,6 +37,8 @@ class VHD2VConverter(Module):
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_params: dict
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_params: dict
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Instance like params (p_ generics, o_ output, ...) when add_instance,
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Instance like params (p_ generics, o_ output, ...) when add_instance,
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generics without prefix otherwise
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generics without prefix otherwise
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_instance: class Instance
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Another instance to convert
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_add_instance: bool
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_add_instance: bool
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add if True an Instance()
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add if True an Instance()
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_force_convert: bool
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_force_convert: bool
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@ -46,11 +48,12 @@ class VHD2VConverter(Module):
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_libraries: list of str or tuple
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_libraries: list of str or tuple
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list of libraries (library_name, library_path) to compile before conversion.
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list of libraries (library_name, library_path) to compile before conversion.
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"""
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"""
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def __init__(self, platform, top_entity, build_dir,
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def __init__(self, platform, top_entity=None, build_dir=None,
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work_package = None,
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work_package = None,
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force_convert = False,
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force_convert = False,
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add_instance = False,
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add_instance = False,
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params = dict(),
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params = None,
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instance = None,
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files = list(),
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files = list(),
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libraries = list()):
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libraries = list()):
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"""
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"""
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@ -62,11 +65,17 @@ class VHD2VConverter(Module):
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self._platform = platform
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self._platform = platform
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self._sources = files
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self._sources = files
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self._params = params
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self._params = params
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self._instance = instance
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self._force_convert = force_convert
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self._force_convert = force_convert
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self._add_instance = add_instance
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self._add_instance = add_instance
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self._work_package = work_package
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self._work_package = work_package
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self._libraries = list()
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self._libraries = list()
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assert (self._params is None) ^ (self._instance is None)
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if self._instance is not None and self._top_entity is None:
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self._top_entity = self._instance.name_override
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self._ghdl_opts = ["--std=08", "--no-formal"]
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self._ghdl_opts = ["--std=08", "--no-formal"]
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if work_package is not None:
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if work_package is not None:
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@ -124,6 +133,9 @@ class VHD2VConverter(Module):
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"""
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"""
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inst_name = self._top_entity
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inst_name = self._top_entity
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if self._build_dir is None:
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self._build_dir = os.path.join(os.path.abspath(self._platform.output_dir), "vhd2v")
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# platform able to synthesis verilog and vhdl -> no conversion
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# platform able to synthesis verilog and vhdl -> no conversion
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if self._platform.support_mixed_language and not self._force_convert:
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if self._platform.support_mixed_language and not self._force_convert:
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ip_params = self._params
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ip_params = self._params
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@ -159,13 +171,21 @@ class VHD2VConverter(Module):
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verilog_out = os.path.join(self._build_dir, f"{inst_name}.v")
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verilog_out = os.path.join(self._build_dir, f"{inst_name}.v")
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ip_params = dict()
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generics = []
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generics = []
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for k, v in self._params.items():
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if self._params:
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if k.startswith("p_"):
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ip_params = dict()
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generics.append("-g" + k[2:] + "=" + str(v))
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for k, v in self._params.items():
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else:
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if k.startswith("p_"):
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ip_params[k] = v
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generics.append("-g" + k[2:] + "=" + str(v))
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else:
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ip_params[k] = v
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else:
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ip_params = list()
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for item in self._instance.items:
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if isinstance(item, Instance.Parameter):
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generics.append("-g" + item.name + "=" + str(item.value.value))
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else:
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ip_params.append(item)
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cmd = ["ghdl", "--synth", "--out=verilog"]
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cmd = ["ghdl", "--synth", "--out=verilog"]
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cmd += self._ghdl_opts
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cmd += self._ghdl_opts
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@ -185,4 +205,9 @@ class VHD2VConverter(Module):
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self._platform.add_source(verilog_out)
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self._platform.add_source(verilog_out)
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if self._add_instance:
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if self._add_instance:
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self.specials += Instance(inst_name, **ip_params)
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if self._instance:
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# remove current instance to avoid multiple definition
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delattr(self, "_instance")
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self.specials += Instance(inst_name, *ip_params)
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else:
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self.specials += Instance(inst_name, **ip_params)
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