transport: generate sop on RX path
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a0cb0c6474
commit
623a3883c6
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@ -94,7 +94,7 @@ class CommandLogger(Module):
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self.packet.read = selfp.sink.read
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self.packet.read = selfp.sink.read
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self.packet.identify = selfp.sink.identify
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self.packet.identify = selfp.sink.identify
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self.packet.sucess = selfp.sink.success
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self.packet.sucess = selfp.sink.success
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self.paclet.failed = selfp.sink.failed
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self.packet.failed = selfp.sink.failed
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self.packet.append(selfp.sink.data)
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self.packet.append(selfp.sink.data)
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elif selfp.sink.stb:
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elif selfp.sink.stb:
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self.packet.append(selfp.sink.data)
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self.packet.append(selfp.sink.data)
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@ -149,6 +149,8 @@ class SATATransportRX(Module):
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fsm = FSM(reset_state="IDLE")
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.submodules += fsm
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data_sop = Signal()
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fsm.act("IDLE",
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fsm.act("IDLE",
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clr_cnt.eq(1),
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clr_cnt.eq(1),
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If(link.source.stb & link.source.sop,
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If(link.source.stb & link.source.sop,
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@ -175,6 +177,8 @@ class SATATransportRX(Module):
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)
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)
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fsm.act("PRESENT_REG_D2H_CMD",
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fsm.act("PRESENT_REG_D2H_CMD",
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source.stb.eq(1),
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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_decode_cmd(encoded_cmd, fis_reg_d2h_layout, source),
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_decode_cmd(encoded_cmd, fis_reg_d2h_layout, source),
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If(source.ack,
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If(source.ack,
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NextState("IDLE")
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NextState("IDLE")
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@ -189,6 +193,8 @@ class SATATransportRX(Module):
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)
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)
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fsm.act("PRESENT_DMA_ACTIVATE_D2H_CMD",
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fsm.act("PRESENT_DMA_ACTIVATE_D2H_CMD",
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source.stb.eq(1),
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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_decode_cmd(encoded_cmd, fis_dma_activate_d2h_layout, source),
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_decode_cmd(encoded_cmd, fis_dma_activate_d2h_layout, source),
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If(source.ack,
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If(source.ack,
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NextState("IDLE")
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NextState("IDLE")
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@ -205,7 +211,7 @@ class SATATransportRX(Module):
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data_receive.eq(1),
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data_receive.eq(1),
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source.stb.eq(link.source.stb),
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source.stb.eq(link.source.stb),
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_decode_cmd(encoded_cmd, fis_data_layout, source),
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_decode_cmd(encoded_cmd, fis_data_layout, source),
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source.sop.eq(0), # XXX
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source.sop.eq(data_sop),
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source.eop.eq(link.source.eop),
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source.eop.eq(link.source.eop),
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source.data.eq(link.source.d),
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source.data.eq(link.source.d),
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If(source.stb & source.eop & source.ack,
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If(source.stb & source.eop & source.ack,
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@ -213,6 +219,15 @@ class SATATransportRX(Module):
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)
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)
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)
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)
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self.sync += \
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If(fsm.ongoing("RECEIVE_DATA_CMD"),
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data_sop.eq(1)
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).Elif(fsm.ongoing("PRESENT_DATA"),
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If(source.stb & source.ack,
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data_sop.eq(0)
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)
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)
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cmd_cases = {}
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cmd_cases = {}
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for i in range(cmd_ndwords):
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for i in range(cmd_ndwords):
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cmd_cases[i] = [encoded_cmd[32*i:32*(i+1)].eq(link.source.d)]
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cmd_cases[i] = [encoded_cmd[32*i:32*(i+1)].eq(link.source.d)]
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