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mac: use eth_phy_description inside mac

This commit is contained in:
Florent Kermarrec 2015-01-28 22:49:49 +01:00
parent 98b82348e7
commit 6249209f94
4 changed files with 10 additions and 10 deletions
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8
liteeth/mac/core/__init__.py
View File

@ -29,14 +29,14 @@ class LiteEthMACCore(Module, AutoCSR):
# Converters # Converters
reverse = endianness == "be" reverse = endianness == "be"
tx_converter = Converter(eth_mac_description(dw), eth_mac_description(phy.dw), reverse=reverse) tx_converter = Converter(eth_phy_description(dw), eth_phy_description(phy.dw), reverse=reverse)
rx_converter = Converter(eth_mac_description(phy.dw), eth_mac_description(dw), reverse=reverse) rx_converter = Converter(eth_phy_description(phy.dw), eth_phy_description(dw), reverse=reverse)
self.submodules += RenameClockDomains(tx_converter, "eth_tx") self.submodules += RenameClockDomains(tx_converter, "eth_tx")
self.submodules += RenameClockDomains(rx_converter, "eth_rx") self.submodules += RenameClockDomains(rx_converter, "eth_rx")
# Cross Domain Crossing # Cross Domain Crossing
tx_cdc = AsyncFIFO(eth_mac_description(dw), 4) tx_cdc = AsyncFIFO(eth_phy_description(dw), 4)
rx_cdc = AsyncFIFO(eth_mac_description(dw), 4) rx_cdc = AsyncFIFO(eth_phy_description(dw), 4)
self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"}) self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"}) self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})

4
liteeth/mac/core/last_be.py
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@ -3,7 +3,7 @@ from liteeth.mac.common import *
class LiteEthMACTXLastBE(Module): class LiteEthMACTXLastBE(Module):
def __init__(self, dw): def __init__(self, dw):
self.sink = sink = Sink(eth_mac_description(dw)) self.sink = sink = Sink(eth_phy_description(dw))
self.source = source = Source(eth_phy_description(dw)) self.source = source = Source(eth_phy_description(dw))
### ###
ongoing = Signal() ongoing = Signal()
@ -26,7 +26,7 @@ class LiteEthMACTXLastBE(Module):
class LiteEthMACRXLastBE(Module): class LiteEthMACRXLastBE(Module):
def __init__(self, dw): def __init__(self, dw):
self.sink = sink = Sink(eth_phy_description(dw)) self.sink = sink = Sink(eth_phy_description(dw))
self.source = source = Source(eth_mac_description(dw)) self.source = source = Source(eth_phy_description(dw))
### ###
self.comb += [ self.comb += [
source.stb.eq(sink.stb), source.stb.eq(sink.stb),

4
liteeth/mac/frontend/sram.py
View File

@ -6,7 +6,7 @@ from migen.bank.eventmanager import *
class LiteEthMACSRAMWriter(Module, AutoCSR): class LiteEthMACSRAMWriter(Module, AutoCSR):
def __init__(self, dw, depth, nslots=2): def __init__(self, dw, depth, nslots=2):
self.sink = sink = Sink(eth_mac_description(dw)) self.sink = sink = Sink(eth_phy_description(dw))
self.crc_error = Signal() self.crc_error = Signal()
slotbits = max(log2_int(nslots), 1) slotbits = max(log2_int(nslots), 1)
@ -131,7 +131,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
class LiteEthMACSRAMReader(Module, AutoCSR): class LiteEthMACSRAMReader(Module, AutoCSR):
def __init__(self, dw, depth, nslots=2): def __init__(self, dw, depth, nslots=2):
self.source = source = Source(eth_mac_description(dw)) self.source = source = Source(eth_phy_description(dw))
slotbits = max(log2_int(nslots), 1) slotbits = max(log2_int(nslots), 1)
lengthbits = log2_int(depth*4) # length in bytes lengthbits = log2_int(depth*4) # length in bytes

4
liteeth/mac/frontend/wishbone.py
View File

@ -7,8 +7,8 @@ from migen.fhdl.simplify import FullMemoryWE
class LiteEthMACWishboneInterface(Module, AutoCSR): class LiteEthMACWishboneInterface(Module, AutoCSR):
def __init__(self, dw, nrxslots=2, ntxslots=2): def __init__(self, dw, nrxslots=2, ntxslots=2):
self.sink = Sink(eth_mac_description(dw)) self.sink = Sink(eth_phy_description(dw))
self.source = Source(eth_mac_description(dw)) self.source = Source(eth_phy_description(dw))
self.bus = wishbone.Interface() self.bus = wishbone.Interface()
### ###
# storage in SRAM # storage in SRAM