mac: use eth_phy_description inside mac
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@ -29,14 +29,14 @@ class LiteEthMACCore(Module, AutoCSR):
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# Converters
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reverse = endianness == "be"
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tx_converter = Converter(eth_mac_description(dw), eth_mac_description(phy.dw), reverse=reverse)
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rx_converter = Converter(eth_mac_description(phy.dw), eth_mac_description(dw), reverse=reverse)
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tx_converter = Converter(eth_phy_description(dw), eth_phy_description(phy.dw), reverse=reverse)
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rx_converter = Converter(eth_phy_description(phy.dw), eth_phy_description(dw), reverse=reverse)
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self.submodules += RenameClockDomains(tx_converter, "eth_tx")
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self.submodules += RenameClockDomains(rx_converter, "eth_rx")
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# Cross Domain Crossing
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tx_cdc = AsyncFIFO(eth_mac_description(dw), 4)
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rx_cdc = AsyncFIFO(eth_mac_description(dw), 4)
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tx_cdc = AsyncFIFO(eth_phy_description(dw), 4)
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rx_cdc = AsyncFIFO(eth_phy_description(dw), 4)
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self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
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self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
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@ -3,7 +3,7 @@ from liteeth.mac.common import *
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class LiteEthMACTXLastBE(Module):
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def __init__(self, dw):
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self.sink = sink = Sink(eth_mac_description(dw))
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self.sink = sink = Sink(eth_phy_description(dw))
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self.source = source = Source(eth_phy_description(dw))
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###
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ongoing = Signal()
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@ -26,7 +26,7 @@ class LiteEthMACTXLastBE(Module):
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class LiteEthMACRXLastBE(Module):
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def __init__(self, dw):
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self.sink = sink = Sink(eth_phy_description(dw))
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self.source = source = Source(eth_mac_description(dw))
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self.source = source = Source(eth_phy_description(dw))
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###
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self.comb += [
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source.stb.eq(sink.stb),
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@ -6,7 +6,7 @@ from migen.bank.eventmanager import *
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class LiteEthMACSRAMWriter(Module, AutoCSR):
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def __init__(self, dw, depth, nslots=2):
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self.sink = sink = Sink(eth_mac_description(dw))
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self.sink = sink = Sink(eth_phy_description(dw))
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self.crc_error = Signal()
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slotbits = max(log2_int(nslots), 1)
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@ -131,7 +131,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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class LiteEthMACSRAMReader(Module, AutoCSR):
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def __init__(self, dw, depth, nslots=2):
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self.source = source = Source(eth_mac_description(dw))
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self.source = source = Source(eth_phy_description(dw))
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slotbits = max(log2_int(nslots), 1)
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lengthbits = log2_int(depth*4) # length in bytes
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@ -7,8 +7,8 @@ from migen.fhdl.simplify import FullMemoryWE
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class LiteEthMACWishboneInterface(Module, AutoCSR):
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def __init__(self, dw, nrxslots=2, ntxslots=2):
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self.sink = Sink(eth_mac_description(dw))
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self.source = Source(eth_mac_description(dw))
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self.sink = Sink(eth_phy_description(dw))
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self.source = Source(eth_phy_description(dw))
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self.bus = wishbone.Interface()
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###
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# storage in SRAM
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