cores/video: Fix depth checks that have to be done in Python, not in logic.
Fixes https://github.com/enjoy-digital/litex/issues/1198.
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@ -656,10 +656,11 @@ class VideoFrameBuffer(Module, AutoCSR):
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# ... and then Clock Domain Crossing.
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# ... and then Clock Domain Crossing.
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self.submodules.cdc = stream.ClockDomainCrossing([("data", depth)], cd_from="sys", cd_to=clock_domain)
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self.submodules.cdc = stream.ClockDomainCrossing([("data", depth)], cd_from="sys", cd_to=clock_domain)
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self.comb += self.conv.source.connect(self.cdc.sink)
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self.comb += self.conv.source.connect(self.cdc.sink)
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self.comb += If((dram_port.data_width < depth) and (depth == 32), # FIXME.
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if (dram_port.data_width < depth) and (depth == 32): # FIXME.
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self.cdc.sink.data[ 0: 8].eq(self.conv.source.data[16:24]),
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self.comb += [
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self.cdc.sink.data[16:24].eq(self.conv.source.data[ 0: 8]),
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self.cdc.sink.data[ 0: 8].eq(self.conv.source.data[16:24]),
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)
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self.cdc.sink.data[16:24].eq(self.conv.source.data[ 0: 8]),
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]
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video_pipe_source = self.cdc.source
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video_pipe_source = self.cdc.source
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# Video Generation.
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# Video Generation.
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@ -671,16 +672,19 @@ class VideoFrameBuffer(Module, AutoCSR):
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),
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),
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vtg_sink.connect(source, keep={"de", "hsync", "vsync"}),
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vtg_sink.connect(source, keep={"de", "hsync", "vsync"}),
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If(depth == 32,
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]
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if (depth == 32):
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self.comb += [
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source.r.eq(video_pipe_source.data[16:24]),
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source.r.eq(video_pipe_source.data[16:24]),
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source.g.eq(video_pipe_source.data[ 8:16]),
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source.g.eq(video_pipe_source.data[ 8:16]),
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source.b.eq(video_pipe_source.data[ 0: 8]),
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source.b.eq(video_pipe_source.data[ 0: 8]),
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).Else( # depth == 16
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]
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else: # depth == 16
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self.comb += [
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source.r.eq(Cat(Signal(3, reset = 0), video_pipe_source.data[ 0: 5])),
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source.r.eq(Cat(Signal(3, reset = 0), video_pipe_source.data[ 0: 5])),
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source.g.eq(Cat(Signal(2, reset = 0), video_pipe_source.data[ 5:11])),
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source.g.eq(Cat(Signal(2, reset = 0), video_pipe_source.data[ 5:11])),
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source.b.eq(Cat(Signal(3, reset = 0), video_pipe_source.data[11:16])),
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source.b.eq(Cat(Signal(3, reset = 0), video_pipe_source.data[11:16])),
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)
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]
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]
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# Underflow.
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# Underflow.
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self.comb += self.underflow.eq(~source.valid)
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self.comb += self.underflow.eq(~source.valid)
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