Merge pull request #543 from antmicro/jboc/eeprom-sim
litex/build/sim: add module for simulating SPD EEPROM
This commit is contained in:
enjoy-digital
GitHub
commit
62d939e85f
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@ -1,5 +1,5 @@
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include ../variables.mak
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MODULES = xgmii_ethernet ethernet serial2console serial2tcp clocker
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MODULES = xgmii_ethernet ethernet serial2console serial2tcp clocker spdeeprom
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.PHONY: $(MODULES)
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all: $(MODULES)
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@ -0,0 +1,2 @@
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include ../../variables.mak
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include $(SRC_DIR)/modules/rules.mak
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@ -0,0 +1,428 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "error.h"
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#include "modules.h"
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/*
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* This is a simulation of SPD EEPROM I2C slave.
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* It only supports basic read/write commands.
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* Although it has been written with SPD EEPROM chips in mind, it should be
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* compatible with some other EEPROM chips that use single byte addressing.
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*
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* Some details can be controlled using defines/environmental variables:
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* #define SPD_EEPROM_ADDR 7bit address of I2C slave
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* #define DEBUG_SPD_EEPROM print debug messages
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* env SPD_EEPROM_FILE load memory contents from file
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*/
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#define SPD_EEPROM_ADDR 0b000
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#ifdef DEBUG_SPD_EEPROM
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#define DBG(...) do{ fprintf(stderr, __VA_ARGS__); } while(0)
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#else
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#define DBG(...) do{ } while (0)
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#endif
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// state of the serial-to-parallel FSM
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enum SerialState {
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IDLE,
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WRITE, // slave writing a byte to master
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READ, // slave reading a byte from master
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RACK_0, // slave starts sending ACK
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RACK_1, // slave finishes sending ACK
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WACK, // slave reads ACK
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};
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// state of the transaction FSM
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enum TransactionState {
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DEV_ADDR, // reading slave device address
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WRITE_ADDR, // master writes address
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WRITE_DATA, // master writes data
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READ_DATA, // master reads data
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};
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// module state
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struct session_s {
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// DUT pads (need separate SDA io/out as Verilator does not support tristate pins)
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char *sys_clk;
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char *sda_in;
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char *sda_out;
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char *scl;
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// SPD EEPROM memory contents
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unsigned char mem[256];
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// state machine
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enum TransactionState state_transaction;
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enum SerialState state_serial;
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unsigned int byte_in;
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unsigned int byte_out;
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unsigned int bit_counter;
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unsigned int devaddr;
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unsigned int addr;
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};
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// Module interface
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static int spdeeprom_start();
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static int spdeeprom_new(void **sess, char *args);
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static int spdeeprom_add_pads(void *sess, struct pad_list_s *plist);
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static int spdeeprom_tick(void *sess);
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// EEPROM simulation
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static void fsm_tick(struct session_s *s);
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static enum SerialState state_serial_next(struct session_s *s);
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// Helper functions
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static void spdeeprom_from_file(struct session_s *s, FILE *file);
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static int litex_sim_module_pads_get(struct pad_s *pads, char *name, void **signal);
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/*** Module interface *****************************************************************************/
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static struct ext_module_s ext_mod = {
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"spdeeprom",
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spdeeprom_start,
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spdeeprom_new,
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spdeeprom_add_pads,
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NULL,
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spdeeprom_tick
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};
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int litex_sim_ext_module_init(int (*register_module)(struct ext_module_s *))
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{
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int ret = RC_OK;
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ret = register_module(&ext_mod);
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return ret;
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}
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static int spdeeprom_start()
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{
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printf("[spdeeprom] loaded (addr = 0x%01x)\n", SPD_EEPROM_ADDR);
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return RC_OK;
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}
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static int spdeeprom_new(void **sess, char *args)
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{
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int ret=RC_OK;
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int i;
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char *spd_filename;
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FILE *spd_file;
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struct session_s *s=NULL;
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if(!sess) {
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ret = RC_INVARG;
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goto out;
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}
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s = (struct session_s*) malloc(sizeof(struct session_s));
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if(!s) {
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ret=RC_NOENMEM;
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goto out;
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}
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memset(s, 0, sizeof(struct session_s));
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spd_filename = getenv("SPD_EEPROM_FILE");
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if (spd_filename != NULL) {
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spd_file = fopen(spd_filename, "r");
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}
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if (spd_filename != NULL && spd_file != NULL) {
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DBG("[spdeeprom] loading EEPROM contents from file: %s\n", spd_filename);
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spdeeprom_from_file(s, spd_file);
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fclose(spd_file);
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} else { // fill in the memory with some data
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for (i = 0; i < sizeof(s->mem) / sizeof(s->mem[0]); ++i) {
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s->mem[i] = i & 0xff;
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}
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}
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out:
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*sess = (void*) s;
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return ret;
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}
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static int spdeeprom_add_pads(void *sess, struct pad_list_s *plist)
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{
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int ret = RC_OK;
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struct session_s *s = (struct session_s*) sess;
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struct pad_s *pads;
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if(!sess || !plist) {
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ret = RC_INVARG;
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goto out;
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}
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pads = plist->pads;
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if(!strcmp(plist->name, "i2c")) {
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litex_sim_module_pads_get(pads, "sda_in", (void**) &s->sda_in);
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litex_sim_module_pads_get(pads, "sda_out", (void**) &s->sda_out);
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litex_sim_module_pads_get(pads, "scl", (void**) &s->scl);
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}
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if(!strcmp(plist->name, "sys_clk"))
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litex_sim_module_pads_get(pads, "sys_clk", (void**) &s->sys_clk);
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out:
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return ret;
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}
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static int spdeeprom_tick(void *sess)
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{
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struct session_s *s = (struct session_s*) sess;
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if (s->sda_in == 0 || s->sda_out == 0 || s->scl == 0) {
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return RC_OK;
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}
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if(*s->sys_clk == 0) {
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return RC_OK;
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}
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fsm_tick(s);
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return RC_OK;
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}
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/*** Simulation ***********************************************************************************/
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#ifdef DEBUG_SPD_EEPROM
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static inline const char *state_serial_str(enum SerialState s)
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{
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switch (s) {
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case IDLE: return "IDLE";
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case WRITE: return "WRITE";
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case READ: return "READ";
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case RACK_0: return "RACK_0";
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case RACK_1: return "RACK_1";
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case WACK: return "WACK";
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default: return "_";
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}
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}
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static inline const char *state_transaction_str(enum TransactionState s)
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{
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switch (s) {
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case DEV_ADDR: return "DEV_ADDR";
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case WRITE_ADDR: return "WRITE_ADDR";
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case WRITE_DATA: return "WRITE_DATA";
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case READ_DATA: return "READ_DATA";
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default: return "_";
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}
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}
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#endif
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static void fsm_tick(struct session_s *s)
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{
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static int sda_last = 1;
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static int scl_last = 1;
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enum SerialState last_state_serial;
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int sda_rising_edge;
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int sda_falling_edge;
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int start_cond;
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int stop_cond;
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int scl_rising;
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int scl_falling;
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sda_rising_edge = !sda_last && *s->sda_out;
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sda_falling_edge = sda_last && !*s->sda_out;
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start_cond = sda_falling_edge && *s->scl;
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stop_cond = sda_rising_edge && *s->scl;
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scl_rising = !scl_last && *s->scl;
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scl_falling = scl_last && !*s->scl;
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sda_last = *s->sda_out;
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scl_last = *s->scl;
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if (start_cond) {
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DBG("[spdeeprom] START condition\n");
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s->state_serial = READ;
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s->state_transaction = DEV_ADDR;
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s->bit_counter = 0;
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}
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if (stop_cond) {
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DBG("[spdeeprom] STOP condition\n");
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s->state_serial = IDLE;
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s->state_transaction = DEV_ADDR;
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}
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last_state_serial = s->state_serial;
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switch (s->state_serial) {
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case IDLE:
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*s->sda_in = 1;
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break;
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case READ:
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if (s->bit_counter == 0) {
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s->byte_in = 0;
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}
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if (scl_rising) {
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s->byte_in <<= 1;
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s->byte_in |= *s->sda_out & 1;
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s->bit_counter++;
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}
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if (s->bit_counter >= 8) {
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s->bit_counter = 0;
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s->state_serial = RACK_0;
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}
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break;
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case WRITE:
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if (scl_rising) {
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*s->sda_in = (s->byte_out & (1 << 7)) != 0;
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s->byte_out <<= 1;
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s->bit_counter++;
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}
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if (s->bit_counter >= 8) {
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s->bit_counter = 0;
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s->state_serial = WACK;
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}
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break;
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case RACK_0: // first falling edge
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if (scl_falling) {
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*s->sda_in = 0;
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s->state_serial = RACK_1;
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}
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break;
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case RACK_1: // second falling edge
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if (scl_falling) {
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*s->sda_in = 1;
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s->state_serial = state_serial_next(s);
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}
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break;
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case WACK:
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if (scl_rising) {
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if ((*s->sda_out) != 0) {
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DBG("[spdeeprom] No ACK from master!\n");
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}
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s->state_serial = state_serial_next(s);
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}
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break;
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default: DBG("[spdeeprom] unknown state_serial\n"); break;
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}
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if (s->state_serial != last_state_serial) {
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DBG("[spdeeprom] state_serial: %s -> %s\n",
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state_serial_str(last_state_serial), state_serial_str(s->state_serial));
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}
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}
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static enum SerialState state_serial_next(struct session_s *s)
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{
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enum TransactionState state_transaction_last = s->state_transaction;
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enum SerialState state_serial = IDLE;
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switch (s->state_transaction) {
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case DEV_ADDR:
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if (s->state_serial != RACK_1) {
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DBG("[spdeeprom] ERROR: DEV_ADDR during WACK\n");
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}
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s->devaddr = s->byte_in;
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if (((s->devaddr & 0b1110) >> 1) != SPD_EEPROM_ADDR) {
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DBG("[spdeeprom] ERROR: read wrong address\n");
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state_serial = IDLE;
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} else {
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DBG("[spdeeprom] devaddr = 0x%02x\n", s->devaddr);
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if ((s->devaddr & 1) != 0) { // read command
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DBG("[spdeeprom] registered READ cmd\n");
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s->state_transaction = READ_DATA;
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s->byte_out = s->mem[s->addr++];
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s->addr %= sizeof(s->mem);
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state_serial = WRITE;
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} else { // write command
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DBG("[spdeeprom] registered WRITE cmd\n");
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s->state_transaction = WRITE_ADDR;
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state_serial = READ;
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}
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}
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break;
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case WRITE_ADDR:
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if (s->state_serial != RACK_1) {
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DBG("[spdeeprom] ERROR: WRITE_ADDR during WACK\n");
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}
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s->addr = s->byte_in;
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s->state_transaction = WRITE_DATA;
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DBG("[spdeeprom] addr = 0x%02x\n", s->addr);
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state_serial = READ;
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break;
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case WRITE_DATA:
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if (s->state_serial != RACK_1) {
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DBG("[spdeeprom] ERROR: WRITE_DATA during WACK\n");
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}
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s->mem[s->addr++] = s->byte_in;
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s->addr %= sizeof(s->mem);
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s->state_transaction = WRITE_DATA;
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DBG("[spdeeprom] wdata = 0x%02x\n", s->byte_in);
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state_serial = READ;
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break;
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case READ_DATA:
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if (s->state_serial != WACK) {
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DBG("[spdeeprom] ERROR: READ_DATA during RACK\n");
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}
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s->state_transaction = READ_DATA;
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s->byte_out = s->mem[s->addr++];
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DBG("[spdeeprom] rdata = 0x%02x\n", s->byte_out);
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state_serial = WRITE;
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break;
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default:
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DBG("[spdeeprom] ERROR: wrong state_transaction!\n");
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break;
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}
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if (state_serial == IDLE) {
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DBG("[spdeeprom] ERROR: unhandled state_serial_next\n");
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}
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if (state_transaction_last != s->state_transaction) {
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DBG("[spdeeprom] state_transaction: %s -> %s\n", state_transaction_str(state_transaction_last), state_transaction_str(s->state_transaction));
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}
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return state_serial;
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}
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/*** Helper functions *****************************************************************************/
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static void spdeeprom_from_file(struct session_s *s, FILE *file)
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{
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size_t bufsize = 0;
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ssize_t n_read;
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char *line = NULL;
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char *c;
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unsigned int byte;
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int i;
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for (i = 0; i < sizeof(s->mem) / sizeof(s->mem[0]); ++i) {
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if ((n_read = getline(&line, &bufsize, file)) < 0) {
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break;
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}
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byte = strtoul(line, &c, 0);
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if (c == line) {
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DBG("[spdeeprom] Incorrect value at line %d\n", i);
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} else {
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s->mem[i] = byte;
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}
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}
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if (line != NULL)
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free(line);
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}
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static int litex_sim_module_pads_get(struct pad_s *pads, char *name, void **signal)
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{
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int ret;
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void *sig=NULL;
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int i;
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if(!pads || !name || !signal) {
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ret = RC_INVARG;
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goto out;
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}
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i = 0;
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while(pads[i].name) {
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if(!strcmp(pads[i].name, name))
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{
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sig = (void*) pads[i].signal;
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break;
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}
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i++;
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}
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out:
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*signal = sig;
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return ret;
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}
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@ -30,8 +30,9 @@ class I2CMaster(Module, AutoCSR):
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CSRField("sda", size=1, offset=0)],
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name="r")
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# # #
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self.connect(pads)
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def connect(self, pads):
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_sda_w = Signal()
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_sda_oe = Signal()
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_sda_r = Signal()
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@ -44,6 +45,32 @@ class I2CMaster(Module, AutoCSR):
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self.specials += Tristate(pads.sda, _sda_w, _sda_oe, _sda_r)
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class I2CMasterSim(I2CMaster):
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"""I2C Master Bit-Banging for Verilator simulation
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Uses separate pads for SDA IN/OUT as Verilator does not support tristate pins well.
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"""
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pads_layout = [("scl", 1), ("sda_in", 1), ("sda_out", 1)]
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def connect(self, pads):
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_sda_w = Signal()
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_sda_oe = Signal()
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_sda_r = Signal()
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_sda_in = Signal()
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self.comb += [
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pads.scl.eq(self._w.fields.scl),
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_sda_oe.eq( self._w.fields.oe),
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_sda_w.eq( self._w.fields.sda),
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If(_sda_oe,
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pads.sda_out.eq(_sda_w),
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self._r.fields.sda.eq(_sda_w),
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).Else(
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pads.sda_out.eq(1),
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self._r.fields.sda.eq(pads.sda_in),
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)
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]
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# SPI Master Bit-Banging ---------------------------------------------------------------------------
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class SPIMaster(Module, AutoCSR):
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@ -18,6 +18,7 @@ from litex.soc.integration.soc_core import *
|
|||
from litex.soc.integration.soc_sdram import *
|
||||
from litex.soc.integration.builder import *
|
||||
from litex.soc.integration.soc import *
|
||||
from litex.soc.cores.bitbang import *
|
||||
|
||||
from litedram import modules as litedram_modules
|
||||
from litedram.modules import parse_spd_hexdump
|
||||
|
|
@ -63,6 +64,11 @@ _io = [
|
|||
Subsignal("sink_ready", Pins(1)),
|
||||
Subsignal("sink_data", Pins(8)),
|
||||
),
|
||||
("i2c", 0,
|
||||
Subsignal("scl", Pins(1)),
|
||||
Subsignal("sda_out", Pins(1)),
|
||||
Subsignal("sda_in", Pins(1)),
|
||||
),
|
||||
]
|
||||
|
||||
# Platform -----------------------------------------------------------------------------------------
|
||||
|
|
@ -170,6 +176,7 @@ class SimSoC(SoCCore):
|
|||
sdram_data_width = 32,
|
||||
sdram_spd_data = None,
|
||||
sdram_verbosity = 0,
|
||||
with_i2c = False,
|
||||
**kwargs):
|
||||
platform = Platform()
|
||||
sys_clk_freq = int(1e6)
|
||||
|
|
@ -293,6 +300,12 @@ class SimSoC(SoCCore):
|
|||
csr_csv = "analyzer.csv")
|
||||
self.add_csr("analyzer")
|
||||
|
||||
# I2C --------------------------------------------------------------------------------------
|
||||
if with_i2c:
|
||||
pads = platform.request("i2c", 0)
|
||||
self.submodules.i2c = I2CMasterSim(pads)
|
||||
self.add_csr("i2c")
|
||||
|
||||
# Build --------------------------------------------------------------------------------------------
|
||||
|
||||
def main():
|
||||
|
|
@ -313,6 +326,7 @@ def main():
|
|||
parser.add_argument("--local-ip", default="192.168.1.50", help="Local IP address of SoC (default=192.168.1.50)")
|
||||
parser.add_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server (default=192.168.1.100)")
|
||||
parser.add_argument("--with-analyzer", action="store_true", help="Enable Analyzer support")
|
||||
parser.add_argument("--with-i2c", action="store_true", help="Enable I2C support")
|
||||
parser.add_argument("--trace", action="store_true", help="Enable Tracing")
|
||||
parser.add_argument("--trace-fst", action="store_true", help="Enable FST tracing (default=VCD)")
|
||||
parser.add_argument("--trace-start", default=0, help="Cycle to start tracing")
|
||||
|
|
@ -352,12 +366,16 @@ def main():
|
|||
if args.with_ethernet or args.with_etherbone:
|
||||
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": args.remote_ip})
|
||||
|
||||
if args.with_i2c:
|
||||
sim_config.add_module("spdeeprom", "i2c")
|
||||
|
||||
# SoC ------------------------------------------------------------------------------------------
|
||||
soc = SimSoC(
|
||||
with_sdram = args.with_sdram,
|
||||
with_ethernet = args.with_ethernet,
|
||||
with_etherbone = args.with_etherbone,
|
||||
with_analyzer = args.with_analyzer,
|
||||
with_i2c = args.with_i2c,
|
||||
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness),
|
||||
**soc_kwargs)
|
||||
if args.ram_init is not None:
|
||||
|
|
|
|||
Loading…
Reference in New Issue