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use new submodules/specials/clock_domains automatic collection

This commit is contained in:
Florent Kermarrec 2015-01-12 12:44:18 +01:00
parent 4f38b0ef6e
commit 62f55e32cf
3 changed files with 6 additions and 6 deletions
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4
lib/sata/phy/k7/crg.py
View File

@ -8,8 +8,8 @@ class K7SATAPHYCRG(Module):
self.reset = Signal() self.reset = Signal()
self.ready = Signal() self.ready = Signal()
self.clock_domains.cd_sata_tx = ClockDomain() self.cd_sata_tx = ClockDomain()
self.clock_domains.cd_sata_rx = ClockDomain() self.cd_sata_rx = ClockDomain()
# CPLL # CPLL
# (SATA3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps # (SATA3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps

4
lib/sata/test/phy_datapath_tb.py
View File

@ -45,8 +45,8 @@ class CTRL(Module):
class TB(Module): class TB(Module):
def __init__(self): def __init__(self):
# use sys_clk for each clock_domain # use sys_clk for each clock_domain
self.clock_domains.cd_sata_rx = ClockDomain() self.cd_sata_rx = ClockDomain()
self.clock_domains.cd_sata_tx = ClockDomain() self.cd_sata_tx = ClockDomain()
self.comb += [ self.comb += [
self.cd_sata_rx.clk.eq(ClockSignal()), self.cd_sata_rx.clk.eq(ClockSignal()),
self.cd_sata_rx.rst.eq(ResetSignal()), self.cd_sata_rx.rst.eq(ResetSignal()),

4
targets/test.py
View File

@ -19,8 +19,8 @@ from migen.genlib.cdc import *
class _CRG(Module): class _CRG(Module):
def __init__(self, platform): def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain() self.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True) self.cd_por = ClockDomain(reset_less=True)
clk200 = platform.request("clk200") clk200 = platform.request("clk200")
clk200_se = Signal() clk200_se = Signal()