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soc/cores: Minor cosmetic changes.

This commit is contained in:
Florent Kermarrec 2023-10-27 11:29:38 +02:00
parent 48f27707d1
commit 63159aa187
7 changed files with 27 additions and 40 deletions
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3
litex/soc/cores/code_8b10b.py
View File

@ -352,8 +352,7 @@ class StreamEncoder(stream.PipelinedActor):
# # #
# Encoders
encoder = Encoder(nwords, True)
self.submodules += encoder
self.encoder = encoder = Encoder(nwords, True)
# Control
self.comb += encoder.ce.eq(self.pipe_ce)

8
litex/soc/cores/dma.py
View File

@ -92,9 +92,7 @@ class WishboneDMAReader(LiteXModule):
self.comb += self._offset.status.eq(offset)
fsm = FSM(reset_state="IDLE")
fsm = ResetInserter()(fsm)
self.submodules += fsm
self.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
self.comb += fsm.reset.eq(~self._enable.storage)
fsm.act("IDLE",
NextValue(offset, 0),
@ -177,9 +175,7 @@ class WishboneDMAWriter(LiteXModule):
self.comb += self._offset.status.eq(offset)
fsm = FSM(reset_state="IDLE")
fsm = ResetInserter()(fsm)
self.submodules += fsm
self.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
self.comb += fsm.reset.eq(~self._enable.storage)
fsm.act("IDLE",
self.sink.ready.eq(ready_on_idle),

2
litex/soc/cores/esc.py
View File

@ -87,7 +87,7 @@ class ESCDShot(LiteXModule):
esc_pad = Signal() # Or platform.request("X") with X = esc pin name.
from litex.soc.cores.esc import ESCDShot
self.submodules.esc0 = ESCDShot(esc_pad, sys_clk_freq, protocol="DSHOT150")
self.esc0 = ESCDShot(esc_pad, sys_clk_freq, protocol="DSHOT150")
# Test script:
# ------------

7
litex/soc/cores/spi/spi_mmap.py
View File

@ -102,8 +102,7 @@ class SPIMaster(LiteXModule):
clk_settle = WaitTimer(int(sys_clk_freq*clk_settle_time))
self.submodules += clk_settle
clk_fsm = FSM(reset_state="IDLE")
self.submodules += clk_fsm
self.clk_fsm = clk_fsm = FSM(reset_state="IDLE")
clk_fsm.act("IDLE",
If(self.start,
NextState("SETTLE")
@ -686,12 +685,12 @@ class SPIMMAP(LiteXModule):
# Pipelines --------------------------------------------------------------------------------
self.submodules += stream.Pipeline(
self.tx_pipeline = stream.Pipeline(
tx_mmap,
tx_fifo,
tx_rx_engine
)
self.submodules += stream.Pipeline(
self.rx_pipeline = stream.Pipeline(
tx_rx_engine,
rx_fifo,
rx_mmap

7
litex/soc/cores/uart.py
View File

@ -65,9 +65,7 @@ class RS232PHYTX(LiteXModule):
count = Signal(4, reset_less=True)
# Clock Phase Accumulator.
clk_phase_accum = RS232ClkPhaseAccum(tuning_word, mode="tx")
self.submodules += clk_phase_accum
self.clk_phase_accum = clk_phase_accum = RS232ClkPhaseAccum(tuning_word, mode="tx")
# FSM
self.fsm = fsm = FSM(reset_state="IDLE")
@ -113,8 +111,7 @@ class RS232PHYRX(LiteXModule):
count = Signal(4, reset_less=True)
# Clock Phase Accumulator.
clk_phase_accum = RS232ClkPhaseAccum(tuning_word, mode="rx")
self.submodules += clk_phase_accum
self.clk_phase_accum = clk_phase_accum = RS232ClkPhaseAccum(tuning_word, mode="rx")
# Resynchronize pads.rx and generate delayed version.
rx = Signal()

26
litex/soc/cores/usb_fifo.py
View File

@ -207,19 +207,17 @@ class FT245PHYAsynchronous(LiteXModule):
tWR = self.ns(30) # WR# active pulse width (t10)
tMultiReg = 2
# read fifo (FTDI --> SoC)
read_fifo = stream.SyncFIFO(phy_description(dw), fifo_depth)
# Read fifo (FTDI --> SoC).
self.read_fifo = read_fifo = stream.SyncFIFO(phy_description(dw), fifo_depth)
# write fifo (SoC --> FTDI)
write_fifo = stream.SyncFIFO(phy_description(dw), fifo_depth)
# Write fifo (SoC --> FTDI).
self.write_fifo = write_fifo = stream.SyncFIFO(phy_description(dw), fifo_depth)
self.submodules += read_fifo, write_fifo
# sink / source interfaces
# Sink / Source interfaces.
self.sink = write_fifo.sink
self.source = read_fifo.source
# read / write arbitration
# Read / Write arbitration.
wants_write = Signal()
wants_read = Signal()
@ -239,13 +237,11 @@ class FT245PHYAsynchronous(LiteXModule):
read_time_en, max_read_time = anti_starvation(self, read_time)
write_time_en, max_write_time = anti_starvation(self, write_time)
fsm = FSM(reset_state="READ")
self.submodules += fsm
read_done = Signal()
write_done = Signal()
commuting = Signal()
self.fsm = fsm = FSM(reset_state="READ")
fsm.act("READ",
read_time_en.eq(1),
If(wants_write & read_done,
@ -284,9 +280,9 @@ class FT245PHYAsynchronous(LiteXModule):
# read actions
pads.rd_n.reset = 1
read_fsm = FSM(reset_state="IDLE")
self.submodules += read_fsm
read_counter = Signal(8)
self.read_fsm = read_fsm = FSM(reset_state="IDLE")
read_fsm.act("IDLE",
read_done.eq(1),
NextValue(read_counter, 0),
@ -317,9 +313,9 @@ class FT245PHYAsynchronous(LiteXModule):
# write actions
pads.wr_n.reset = 1
write_fsm = FSM(reset_state="IDLE")
self.submodules += write_fsm
write_counter = Signal(8)
self.write_fsm = write_fsm = FSM(reset_state="IDLE")
write_fsm.act("IDLE",
write_done.eq(1),
NextValue(write_counter, 0),

10
litex/soc/cores/video.py
View File

@ -835,7 +835,7 @@ class VideoHDMIPHY(LiteXModule):
for color, channel in _dvi_c2d.items():
# TMDS Encoding.
encoder = ClockDomainsRenamer(clock_domain)(TMDSEncoder())
setattr(self.submodules, f"{color}_encoder", encoder)
self.add_module(name=f"{color}_encoder", module=encoder)
self.comb += encoder.d.eq(getattr(sink, color))
self.comb += encoder.c.eq(Cat(sink.hsync, sink.vsync) if channel == 0 else 0)
self.comb += encoder.de.eq(sink.de)
@ -848,7 +848,7 @@ class VideoHDMIPHY(LiteXModule):
data_o = data_o,
clock_domain = clock_domain,
)
setattr(self.submodules, f"{color}_serializer", serializer)
self.add_module(name=f"{color}_serializer", module=serializer)
# HDMI (Gowin).
@ -872,7 +872,7 @@ class VideoGowinHDMIPHY(LiteXModule):
for color, channel in _dvi_c2d.items():
# TMDS Encoding.
encoder = ClockDomainsRenamer(clock_domain)(TMDSEncoder())
setattr(self.submodules, f"{color}_encoder", encoder)
self.add_module(name=f"{color}_encoder", module=encoder)
self.comb += encoder.d.eq(getattr(sink, color))
self.comb += encoder.c.eq(Cat(sink.hsync, sink.vsync) if channel == 0 else 0)
self.comb += encoder.de.eq(sink.de)
@ -916,7 +916,7 @@ class VideoS6HDMIPHY(LiteXModule):
# TMDS Encoding.
encoder = ClockDomainsRenamer(clock_domain)(TMDSEncoder())
setattr(self.submodules, f"{color}_encoder", encoder)
self.add_module(name=f"{color}_encoder", module=encoder)
self.comb += encoder.d.eq(getattr(sink, color))
self.comb += encoder.c.eq(Cat(sink.hsync, sink.vsync) if channel == 0 else 0)
self.comb += encoder.de.eq(sink.de)
@ -928,7 +928,7 @@ class VideoS6HDMIPHY(LiteXModule):
data_o = pad_o,
clock_domain = clock_domain,
)
setattr(self.submodules, f"{color}_serializer", serializer)
self.add_module(name=f"{color}_serializer", module=serializer)
pad_p = getattr(pads, f"data{channel}_p")
pad_n = getattr(pads, f"data{channel}_n")
self.specials += Instance("OBUFDS", i_I=pad_o, o_O=pad_p, o_OB=pad_n)