cpu/naxriscv: Minor cleanups.
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@ -4,10 +4,10 @@
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# Copyright (c) 2020-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020-2022 Dolu1990 <charles.papon.90@gmail.com>
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# Copyright (c) 2020-2022 Dolu1990 <charles.papon.90@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# SPDX-License-Identifier: BSD-2-Clause
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import hashlib
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import os
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import os
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import hashlib
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import subprocess
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import subprocess
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from os import path
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from migen import *
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from migen import *
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@ -258,7 +258,7 @@ class NaxRiscv(CPU):
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def add_sources(self, platform):
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def add_sources(self, platform):
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vdir = get_data_mod("cpu", "naxriscv").data_location
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vdir = get_data_mod("cpu", "naxriscv").data_location
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print(f"NaxRiscv netlist : {self.netlist_name}")
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print(f"NaxRiscv netlist : {self.netlist_name}")
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if not path.exists(os.path.join(vdir, self.netlist_name + ".v")):
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if not os.path.exists(os.path.join(vdir, self.netlist_name + ".v")):
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self.generate_netlist(self.reset_address)
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self.generate_netlist(self.reset_address)
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# Add RAM.
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# Add RAM.
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@ -364,8 +364,8 @@ class NaxRiscv(CPU):
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debug_ndmreset_last = Signal()
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debug_ndmreset_last = Signal()
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debug_ndmreset_rise = Signal()
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debug_ndmreset_rise = Signal()
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self.cpu_params.update(
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self.cpu_params.update(
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i_debug_reset=debug_reset,
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i_debug_reset = debug_reset,
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o_debug_ndmreset=debug_ndmreset,
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o_debug_ndmreset = debug_ndmreset,
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)
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)
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# Reset SoC's CRG when debug_ndmreset rising edge.
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# Reset SoC's CRG when debug_ndmreset rising edge.
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@ -472,5 +472,5 @@ class NaxRiscv(CPU):
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# Do verilog instance.
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# Do verilog instance.
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self.specials += Instance(self.netlist_name, **self.cpu_params)
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self.specials += Instance(self.netlist_name, **self.cpu_params)
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# Add verilog sources
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# Add verilog sources.
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self.add_sources(self.platform)
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self.add_sources(self.platform)
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