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cpu/naxriscv: Minor cleanups.

This commit is contained in:
Florent Kermarrec 2022-04-14 10:12:45 +02:00
parent 0a738002e0
commit 63356b8187
1 changed files with 7 additions and 7 deletions
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14
litex/soc/cores/cpu/naxriscv/core.py
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@ -4,10 +4,10 @@
# Copyright (c) 2020-2022 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2020-2022 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2020-2022 Dolu1990 <charles.papon.90@gmail.com> # Copyright (c) 2020-2022 Dolu1990 <charles.papon.90@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
import hashlib
import os import os
import hashlib
import subprocess import subprocess
from os import path
from migen import * from migen import *
@ -258,7 +258,7 @@ class NaxRiscv(CPU):
def add_sources(self, platform): def add_sources(self, platform):
vdir = get_data_mod("cpu", "naxriscv").data_location vdir = get_data_mod("cpu", "naxriscv").data_location
print(f"NaxRiscv netlist : {self.netlist_name}") print(f"NaxRiscv netlist : {self.netlist_name}")
if not path.exists(os.path.join(vdir, self.netlist_name + ".v")): if not os.path.exists(os.path.join(vdir, self.netlist_name + ".v")):
self.generate_netlist(self.reset_address) self.generate_netlist(self.reset_address)
# Add RAM. # Add RAM.
@ -360,12 +360,12 @@ class NaxRiscv(CPU):
self.sync.debug_por += debug_reset.eq(0) self.sync.debug_por += debug_reset.eq(0)
# Debug resets. # Debug resets.
debug_ndmreset = Signal() debug_ndmreset = Signal()
debug_ndmreset_last = Signal() debug_ndmreset_last = Signal()
debug_ndmreset_rise = Signal() debug_ndmreset_rise = Signal()
self.cpu_params.update( self.cpu_params.update(
i_debug_reset=debug_reset, i_debug_reset = debug_reset,
o_debug_ndmreset=debug_ndmreset, o_debug_ndmreset = debug_ndmreset,
) )
# Reset SoC's CRG when debug_ndmreset rising edge. # Reset SoC's CRG when debug_ndmreset rising edge.
@ -472,5 +472,5 @@ class NaxRiscv(CPU):
# Do verilog instance. # Do verilog instance.
self.specials += Instance(self.netlist_name, **self.cpu_params) self.specials += Instance(self.netlist_name, **self.cpu_params)
# Add verilog sources # Add verilog sources.
self.add_sources(self.platform) self.add_sources(self.platform)