soc/sata: fix typo in Mem2Sector DMA.

2020-10-30 15:37:20 +01:00 · 2020-10-30 15:37:20 +01:00 · 638d28d8d4
parent 060bbf1d59
commit 638d28d8d4
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -1462,7 +1462,7 @@ class LiteXSoC(SoC):
        # Mem2Sector DMA
        if "write" in mode:
            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
-            self.submodules.sata_sector2mem = LiteSATAMem2SectorDMA(
+            self.submodules.sata_mem2sector = LiteSATAMem2SectorDMA(
               bus        = bus,
               port       = self.sata_crossbar.get_port(),
               endianness = self.cpu.endianness)