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soc/sata: fix typo in Mem2Sector DMA.

This commit is contained in:
Florent Kermarrec 2020-10-30 15:37:20 +01:00
parent 060bbf1d59
commit 638d28d8d4
1 changed files with 1 additions and 1 deletions
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2
litex/soc/integration/soc.py
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@ -1462,7 +1462,7 @@ class LiteXSoC(SoC):
# Mem2Sector DMA # Mem2Sector DMA
if "write" in mode: if "write" in mode:
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width) bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.submodules.sata_sector2mem = LiteSATAMem2SectorDMA( self.submodules.sata_mem2sector = LiteSATAMem2SectorDMA(
bus = bus, bus = bus,
port = self.sata_crossbar.get_port(), port = self.sata_crossbar.get_port(),
endianness = self.cpu.endianness) endianness = self.cpu.endianness)