soc_core: fix cpu_type=None case and add test for it

This commit is contained in:
Florent Kermarrec 2019-09-30 08:26:38 +02:00
parent 3d257d7266
commit 63a813af9c
3 changed files with 11 additions and 0 deletions

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@ -18,6 +18,10 @@ class CPU(Module):
interrupts = {} interrupts = {}
mem_map = {} mem_map = {}
class CPUNone(CPU):
data_width = 32
reset_address = 0x00000000
# CPUS --------------------------------------------------------------------------------------------- # CPUS ---------------------------------------------------------------------------------------------
from litex.soc.cores.cpu.lm32 import LM32 from litex.soc.cores.cpu.lm32 import LM32

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@ -193,6 +193,8 @@ class SoCCore(Module):
# Allow SoCController to reset the CPU # Allow SoCController to reset the CPU
if with_ctrl: if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset) self.comb += self.cpu.reset.eq(self.ctrl.reset)
else:
self.add_cpu(cpu.CPUNone())
# Add user's interrupts (needs to be done after CPU interrupts are allocated) # Add user's interrupts (needs to be done after CPU interrupts are allocated)
for _name, _id in self.interrupt_map.items(): for _name, _id in self.interrupt_map.items():

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@ -121,6 +121,11 @@ litex/boards/targets/simple.py litex.boards.platforms.{p} \
""".format(p=p) """.format(p=p)
subprocess.check_call(cmd, shell=True) subprocess.check_call(cmd, shell=True)
def test_cpu_none(self):
from litex.boards.targets.arty import BaseSoC
errors = build_test([BaseSoC(cpu_type=None)])
self.assertEqual(errors, 0)
def run_variants(self, cpu, variants): def run_variants(self, cpu, variants):
for v in variants: for v in variants:
with self.subTest(cpu=cpu, variant=v): with self.subTest(cpu=cpu, variant=v):