soc_core: fix cpu_type=None case and add test for it
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3d257d7266
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@ -18,6 +18,10 @@ class CPU(Module):
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interrupts = {}
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interrupts = {}
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mem_map = {}
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mem_map = {}
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class CPUNone(CPU):
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data_width = 32
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reset_address = 0x00000000
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# CPUS ---------------------------------------------------------------------------------------------
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# CPUS ---------------------------------------------------------------------------------------------
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from litex.soc.cores.cpu.lm32 import LM32
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from litex.soc.cores.cpu.lm32 import LM32
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@ -193,6 +193,8 @@ class SoCCore(Module):
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# Allow SoCController to reset the CPU
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# Allow SoCController to reset the CPU
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if with_ctrl:
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if with_ctrl:
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self.comb += self.cpu.reset.eq(self.ctrl.reset)
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self.comb += self.cpu.reset.eq(self.ctrl.reset)
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else:
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self.add_cpu(cpu.CPUNone())
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# Add user's interrupts (needs to be done after CPU interrupts are allocated)
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# Add user's interrupts (needs to be done after CPU interrupts are allocated)
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for _name, _id in self.interrupt_map.items():
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for _name, _id in self.interrupt_map.items():
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@ -121,6 +121,11 @@ litex/boards/targets/simple.py litex.boards.platforms.{p} \
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""".format(p=p)
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""".format(p=p)
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subprocess.check_call(cmd, shell=True)
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subprocess.check_call(cmd, shell=True)
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def test_cpu_none(self):
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from litex.boards.targets.arty import BaseSoC
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errors = build_test([BaseSoC(cpu_type=None)])
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self.assertEqual(errors, 0)
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def run_variants(self, cpu, variants):
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def run_variants(self, cpu, variants):
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for v in variants:
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for v in variants:
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with self.subTest(cpu=cpu, variant=v):
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with self.subTest(cpu=cpu, variant=v):
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