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soc/add_ethernet: soc/add_etherbone: Add data_width parameter and allow 8-bit/32-bit core data_width.

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This commit is contained in:
Florent Kermarrec 2022-04-25 18:44:52 +02:00
parent bdbb6c0b3f
commit 63cda6c7b9
1 changed files with 10 additions and 5 deletions
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7
litex/soc/integration/soc.py
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@ -1520,6 +1520,7 @@ class LiteXSoC(SoC):
# Add Ethernet ---------------------------------------------------------------------------------
def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False, software_debug=False,
data_width = 8,
nrxslots = 2,
ntxslots = 2,
with_timestamp = False,
@ -1529,6 +1530,8 @@ class LiteXSoC(SoC):
from liteeth.phy.model import LiteEthPHYModel
# MAC.
assert data_width in [8, 32]
with_sys_datapath = (data_width == 32)
self.check_if_exists(name)
if with_timestamp:
self.timer0.add_uptime()
@ -1540,7 +1543,9 @@ class LiteXSoC(SoC):
nrxslots = nrxslots,
ntxslots = ntxslots,
timestamp = None if not with_timestamp else self.timer0.uptime_cycles,
with_preamble_crc = not software_debug)
with_preamble_crc = not software_debug,
with_sys_datapath = with_sys_datapath)
if not with_sys_datapath:
# Use PHY's eth_tx/eth_rx clock domains.
ethmac = ClockDomainsRenamer({
"eth_tx": phy_cd + "_tx",