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Merge pull request #2086 from VOGL-electronic/build_io_clocksignal 

build: io: don't use mutable object as default value
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enjoy-digital 2024-10-01 11:49:03 +02:00 committed by GitHub
parent 87ee6ec3a0 280b6b4ee4
commit 644ef7e4e5
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GPG Key ID: B5690EEEBB952194
1 changed files with 13 additions and 7 deletions
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20
litex/build/io.py
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@ -83,11 +83,13 @@ class InferedSDRIO(Module):
self.sync.sdrio += o.eq(i) self.sync.sdrio += o.eq(i)
class SDRIO(Special): class SDRIO(Special):
def __init__(self, i, o, clk=ClockSignal()): def __init__(self, i, o, clk=None):
assert len(i) == len(o) == 1 assert len(i) == len(o) == 1
Special.__init__(self) Special.__init__(self)
self.i = wrap(i) self.i = wrap(i)
self.o = wrap(o) self.o = wrap(o)
if clk is None:
clk = ClockSignal()
self.clk = wrap(clk) self.clk = wrap(clk)
self.clk_domain = None if not hasattr(clk, "cd") else clk.cd self.clk_domain = None if not hasattr(clk, "cd") else clk.cd
@ -117,14 +119,14 @@ class InferedSDRTristate(Module):
self.specials += Tristate(io, _o, _oe, _i) self.specials += Tristate(io, _o, _oe, _i)
class SDRTristate(Special): class SDRTristate(Special):
def __init__(self, io, o, oe, i, clk=ClockSignal()): def __init__(self, io, o, oe, i, clk=None):
assert len(i) == len(o) == len(oe) assert len(i) == len(o) == len(oe)
Special.__init__(self) Special.__init__(self)
self.io = wrap(io) self.io = wrap(io)
self.o = wrap(o) self.o = wrap(o)
self.oe = wrap(oe) self.oe = wrap(oe)
self.i = wrap(i) self.i = wrap(i)
self.clk = wrap(clk) self.clk = wrap(clk) if clk is not None else ClockSignal()
def iter_expressions(self): def iter_expressions(self):
yield self, "io" , SPECIAL_INOUT yield self, "io" , SPECIAL_INOUT
@ -140,11 +142,13 @@ class SDRTristate(Special):
# DDR Input/Output --------------------------------------------------------------------------------- # DDR Input/Output ---------------------------------------------------------------------------------
class DDRInput(Special): class DDRInput(Special):
def __init__(self, i, o1, o2, clk=ClockSignal()): def __init__(self, i, o1, o2, clk=None):
Special.__init__(self) Special.__init__(self)
self.i = wrap(i) self.i = wrap(i)
self.o1 = wrap(o1) self.o1 = wrap(o1)
self.o2 = wrap(o2) self.o2 = wrap(o2)
if clk is None:
clk = ClockSignal()
self.clk = clk if isinstance(clk, str) else wrap(clk) self.clk = clk if isinstance(clk, str) else wrap(clk)
def iter_expressions(self): def iter_expressions(self):
@ -159,11 +163,13 @@ class DDRInput(Special):
class DDROutput(Special): class DDROutput(Special):
def __init__(self, i1, i2, o, clk=ClockSignal()): def __init__(self, i1, i2, o, clk=None):
Special.__init__(self) Special.__init__(self)
self.i1 = wrap(i1) self.i1 = wrap(i1)
self.i2 = wrap(i2) self.i2 = wrap(i2)
self.o = wrap(o) self.o = wrap(o)
if clk is None:
clk = ClockSignal()
self.clk = clk if isinstance(clk, str) else wrap(clk) self.clk = clk if isinstance(clk, str) else wrap(clk)
def iter_expressions(self): def iter_expressions(self):
@ -189,7 +195,7 @@ class InferedDDRTristate(Module):
self.specials += Tristate(io, _o, _oe, _i) self.specials += Tristate(io, _o, _oe, _i)
class DDRTristate(Special): class DDRTristate(Special):
def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk=ClockSignal()): def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk=None):
Special.__init__(self) Special.__init__(self)
self.io = io self.io = io
self.o1 = o1 self.o1 = o1
@ -198,7 +204,7 @@ class DDRTristate(Special):
self.oe2 = oe2 self.oe2 = oe2
self.i1 = i1 self.i1 = i1
self.i2 = i2 self.i2 = i2
self.clk = clk self.clk = clk if clk is not None else ClockSignal()
def iter_expressions(self): def iter_expressions(self):
yield self, "io" , SPECIAL_INOUT yield self, "io" , SPECIAL_INOUT