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kc705: enable DCI termination on DDR3

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Florent Kermarrec 2014-09-01 23:11:40 +02:00 committed by Sebastien Bourdeauducq
parent 402c7db63c
commit 644fa8ec55
1 changed files with 5 additions and 1 deletions
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6
mibuild/platforms/kc705.py
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@ -109,7 +109,7 @@ _io = [
"AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1",
"AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5",
"AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"),
IOStandard("SSTL15")),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"),
IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"),
@ -150,4 +150,8 @@ def Platform(*args, toolchain="vivado", **kwargs):
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
except ConstraintError:
pass
if isinstance(self, XilinxISEPlatform):
self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
else:
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
return RealPlatform(*args, **kwargs)