Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/cores/cpu/vexriscv: move verilog variant selection to add_sources

This commit is contained in:
Florent Kermarrec 2019-01-09 08:32:17 +01:00
parent 2b5a6f1058
commit 648015d78e
1 changed files with 11 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
litex/soc/cores/cpu/vexriscv/core.py
View File

@ -24,16 +24,6 @@ class VexRiscv(Module, AutoCSR):
self.interrupt = Signal(32)
verilog_variants = {
"std": "VexRiscv.v",
"std_debug": "VexRiscv_Debug.v",
"lite": "VexRiscv_Lite.v",
"lite_debug": "VexRiscv_LiteDebug.v",
"min": "VexRiscv_Lite.v",
"min_debug": "VexRiscv_LiteDebug.v",
}
cpu_filename = verilog_variants[variant]
self.cpu_params = dict(
i_clk=ClockSignal(),
i_reset=ResetSignal() | self.reset,
@ -70,7 +60,7 @@ class VexRiscv(Module, AutoCSR):
self.add_debug()
# add verilog sources
self.add_sources(platform, cpu_filename)
self.add_sources(platform, variant)
def add_debug(self):
debug_reset = Signal()
@ -159,7 +149,16 @@ class VexRiscv(Module, AutoCSR):
)
@staticmethod
def add_sources(platform, cpu_filename):
def add_sources(platform, variant="std"):
verilog_variants = {
"std": "VexRiscv.v",
"std_debug": "VexRiscv_Debug.v",
"lite": "VexRiscv_Lite.v",
"lite_debug": "VexRiscv_LiteDebug.v",
"min": "VexRiscv_Lite.v",
"min_debug": "VexRiscv_LiteDebug.v",
}
cpu_filename = verilog_variants[variant]
vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_source(os.path.join(vdir, cpu_filename))