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liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen

This commit is contained in:
Florent Kermarrec 2015-03-01 16:45:50 +01:00
parent bd4d3cd73b
commit 649cdeb265
10 changed files with 40 additions and 121 deletions
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2
misoclib/com/liteeth/common.py
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@ -6,7 +6,7 @@ from migen.fhdl.decorators import ModuleDecorator
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.record import *
from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import chooser
from migen.genlib.misc import chooser, FlipFlop, Counter, Timeout
from migen.flow.actor import *
from migen.flow.plumbing import Buffer
from migen.actorlib.structuring import Converter, Pipeline

2
misoclib/com/liteeth/example_designs/targets/base.py
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@ -36,7 +36,7 @@ class BaseSoC(SoC, AutoCSR):
mac_address=0x10e2d5000000,
ip_address="192.168.1.40"):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200)
self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
SoC.__init__(self, platform, clk_freq, self.uart2wb,
with_cpu=False,
with_csr=True, csr_data_width=32,

29
misoclib/com/liteeth/generic/__init__.py
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@ -10,35 +10,6 @@ class Port:
return r
# Generic modules
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
class FlipFlop(Module):
def __init__(self, *args, **kwargs):
self.d = Signal(*args, **kwargs)
self.q = Signal(*args, **kwargs)
self.sync += self.q.eq(self.d)
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
class Counter(Module):
def __init__(self, signal=None, **kwargs):
if signal is None:
self.value = Signal(**kwargs)
else:
self.value = signal
self.width = flen(self.value)
self.sync += self.value.eq(self.value+1)
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
class Timeout(Module):
def __init__(self, length):
self.reached = Signal()
###
value = Signal(max=length)
self.sync += If(~self.reached, value.eq(value+1))
self.comb += self.reached.eq(value == (length-1))
class BufferizeEndpoints(ModuleDecorator):
def __init__(self, submodule, *args):
ModuleDecorator.__init__(self, submodule)

23
misoclib/mem/litesata/common.py
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@ -5,7 +5,7 @@ from migen.fhdl.decorators import ModuleDecorator
from migen.genlib.resetsync import *
from migen.genlib.fsm import *
from migen.genlib.record import *
from migen.genlib.misc import chooser, optree
from migen.genlib.misc import chooser, optree, Counter, Timeout
from migen.genlib.cdc import *
from migen.flow.actor import *
from migen.flow.plumbing import Multiplexer, Demultiplexer
@ -252,27 +252,6 @@ def sectors2dwords(n):
return n*logical_sector_size//4
# Generic modules
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
class Counter(Module):
def __init__(self, signal=None, **kwargs):
if signal is None:
self.value = Signal(**kwargs)
else:
self.value = signal
self.width = flen(self.value)
self.sync += self.value.eq(self.value+1)
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
class Timeout(Module):
def __init__(self, length):
self.reached = Signal()
###
value = Signal(max=length)
self.sync += If(~self.reached, value.eq(value+1))
self.comb += self.reached.eq(value == (length-1))
class BufferizeEndpoints(ModuleDecorator):
def __init__(self, submodule, *args):
ModuleDecorator.__init__(self, submodule)

2
misoclib/mem/litesata/example_designs/targets/bist.py
View File

@ -89,7 +89,7 @@ class BISTSoC(SoC, AutoCSR):
csr_map.update(SoC.csr_map)
def __init__(self, platform):
clk_freq = 166*1000000
self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200)
self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
SoC.__init__(self, platform, clk_freq, self.uart2wb,
with_cpu=False,
with_csr=True, csr_data_width=32,

14
misoclib/mem/litesata/frontend/bist.py
View File

@ -19,7 +19,7 @@ class LiteSATABISTGenerator(Module):
source, sink = user_port.sink, user_port.source
counter = Counter(bits_sign=32)
counter = Counter(32)
self.submodules += counter
scrambler = scrambler = InsertReset(Scrambler())
@ -82,9 +82,10 @@ class LiteSATABISTChecker(Module):
source, sink = user_port.sink, user_port.source
counter = Counter(bits_sign=32)
error_counter = Counter(self.errors, bits_sign=32)
counter = Counter(32)
error_counter = Counter(32)
self.submodules += counter, error_counter
self.comb += self.errors.eq(error_counter.value)
scrambler = InsertReset(Scrambler())
self.submodules += scrambler
@ -178,7 +179,7 @@ class LiteSATABISTUnitCSR(Module, AutoCSR):
]
self.fsm = fsm = FSM(reset_state="IDLE")
loop_counter = Counter(bits_sign=8)
loop_counter = Counter(8)
self.submodules += fsm, loop_counter
fsm.act("IDLE",
self._done.status.eq(1),
@ -205,11 +206,12 @@ class LiteSATABISTUnitCSR(Module, AutoCSR):
)
)
cycles_counter = Counter(self._cycles.status)
cycles_counter = Counter(32)
self.submodules += cycles_counter
self.sync += [
cycles_counter.reset.eq(start),
cycles_counter.ce.eq(~fsm.ongoing("IDLE"))
cycles_counter.ce.eq(~fsm.ongoing("IDLE")),
self._cycles.status.eq(cycles_counter.value)
]
class LiteSATABISTIdentify(Module):

57
misoclib/tools/litescope/bridge/uart2wb.py
View File

@ -7,18 +7,7 @@ from migen.bank.eventmanager import *
from migen.genlib.record import Record
from migen.flow.actor import Sink, Source
from misoclib.com.uart import UARTRX, UARTTX
class UART(Module, AutoCSR):
def __init__(self, pads, clk_freq, baud=115200):
self._tuning_word = CSRStorage(32, reset=int((baud/clk_freq)*2**32))
tuning_word = self._tuning_word.storage
###
self.rx = UARTRX(pads, tuning_word)
self.tx = UARTTX(pads, tuning_word)
self.submodules += self.rx, self.tx
from misoclib.com.uart.phy.serial import UARTPHYSerial
class UARTPads:
def __init__(self):
@ -58,23 +47,23 @@ class LiteScopeUART2WB(Module, AutoCSR):
"write" : 0x01,
"read" : 0x02
}
def __init__(self, pads, clk_freq, baud=115200, share_uart=False):
def __init__(self, pads, clk_freq, baudrate=115200, share_uart=False):
self.wishbone = wishbone.Interface()
if share_uart:
self._sel = CSRStorage()
###
if share_uart:
uart_mux = UARTMux(pads)
uart = UART(uart_mux.bridge_pads, clk_freq, baud)
self.submodules += uart_mux, uart
self.shared_pads = uart_mux.shared_pads
self.comb += uart_mux.sel.eq(self._sel.storage)
mux = UARTMux(pads)
uart = UARTPHYSerial(mux.bridge_pads, clk_freq, baudrate)
self.submodules += mux, uart
self.shared_pads = mux.shared_pads
self.comb += mux.sel.eq(self._sel.storage)
else:
uart = UART(pads, clk_freq, baud)
uart = UARTPHYSerial(pads, clk_freq, baudrate)
self.submodules += uart
byte_counter = Counter(bits_sign=3)
word_counter = Counter(bits_sign=8)
byte_counter = Counter(3)
word_counter = Counter(8)
self.submodules += byte_counter, word_counter
cmd = Signal(8)
@ -91,11 +80,11 @@ class LiteScopeUART2WB(Module, AutoCSR):
tx_data_ce = Signal()
self.sync += [
If(cmd_ce, cmd.eq(uart.rx.source.d)),
If(length_ce, length.eq(uart.rx.source.d)),
If(address_ce, address.eq(Cat(uart.rx.source.d, address[0:24]))),
If(cmd_ce, cmd.eq(uart.source.d)),
If(length_ce, length.eq(uart.source.d)),
If(address_ce, address.eq(Cat(uart.source.d, address[0:24]))),
If(rx_data_ce,
data.eq(Cat(uart.rx.source.d, data[0:24]))
data.eq(Cat(uart.source.d, data[0:24]))
).Elif(tx_data_ce,
data.eq(self.wishbone.dat_r)
)
@ -111,10 +100,10 @@ class LiteScopeUART2WB(Module, AutoCSR):
]
fsm.act("IDLE",
timeout.reset.eq(1),
If(uart.rx.source.stb,
If(uart.source.stb,
cmd_ce.eq(1),
If( (uart.rx.source.d == self.cmds["write"]) |
(uart.rx.source.d == self.cmds["read"]),
If( (uart.source.d == self.cmds["write"]) |
(uart.source.d == self.cmds["read"]),
NextState("RECEIVE_LENGTH")
),
byte_counter.reset.eq(1),
@ -122,13 +111,13 @@ class LiteScopeUART2WB(Module, AutoCSR):
)
)
fsm.act("RECEIVE_LENGTH",
If(uart.rx.source.stb,
If(uart.source.stb,
length_ce.eq(1),
NextState("RECEIVE_ADDRESS")
)
)
fsm.act("RECEIVE_ADDRESS",
If(uart.rx.source.stb,
If(uart.source.stb,
address_ce.eq(1),
byte_counter.ce.eq(1),
If(byte_counter.value == 3,
@ -142,7 +131,7 @@ class LiteScopeUART2WB(Module, AutoCSR):
)
)
fsm.act("RECEIVE_DATA",
If(uart.rx.source.stb,
If(uart.source.stb,
rx_data_ce.eq(1),
byte_counter.ce.eq(1),
If(byte_counter.value == 3,
@ -179,10 +168,10 @@ class LiteScopeUART2WB(Module, AutoCSR):
)
)
self.comb += \
chooser(data, byte_counter.value, uart.tx.sink.d, n=4, reverse=True)
chooser(data, byte_counter.value, uart.sink.d, n=4, reverse=True)
fsm.act("SEND_DATA",
uart.tx.sink.stb.eq(1),
If(uart.tx.sink.ack,
uart.sink.stb.eq(1),
If(uart.sink.ack,
byte_counter.ce.eq(1),
If(byte_counter.value == 3,
word_counter.ce.eq(1),

24
misoclib/tools/litescope/common.py
View File

@ -2,6 +2,7 @@ from migen.fhdl.std import *
from migen.bank.description import *
from migen.genlib.fsm import FSM, NextState
from migen.flow.actor import *
from migen.genlib.misc import Counter, Timeout
from migen.actorlib.fifo import AsyncFIFO, SyncFIFO
from migen.flow.plumbing import Buffer
from migen.fhdl.specials import Memory
@ -11,26 +12,3 @@ def data_layout(dw):
def hit_layout():
return [("hit", 1, DIR_M_TO_S)]
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
class Counter(Module):
def __init__(self, signal=None, **kwargs):
if signal is None:
self.value = Signal(**kwargs)
else:
self.value = signal
self.width = flen(self.value)
self.sync += self.value.eq(self.value+1)
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
class Timeout(Module):
def __init__(self, length):
self.reached = Signal()
###
value = Signal(max=length)
self.sync += value.eq(value+1)
self.comb += [
self.reached.eq(value == length)
]

2
misoclib/tools/litescope/core/storage.py
View File

@ -7,7 +7,7 @@ class LiteScopeSubSamplerUnit(Module):
self.source = source = Source(data_layout(dw))
self.value = Signal(32)
###
self.submodules.counter = Counter(bits_sign=32)
self.submodules.counter = Counter(32)
done = Signal()
self.comb += [
done.eq(self.counter.value >= self.value),

6
misoclib/tools/litescope/example_designs/targets/simple.py
View File

@ -29,7 +29,7 @@ class LiteScopeSoC(SoC, AutoCSR):
csr_map.update(SoC.csr_map)
def __init__(self, platform):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200)
self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
SoC.__init__(self, platform, clk_freq, self.uart2wb,
with_cpu=False,
with_csr=True, csr_data_width=32,
@ -47,8 +47,8 @@ class LiteScopeSoC(SoC, AutoCSR):
except:
pass
self.submodules.counter0 = counter0 = Counter(bits_sign=8)
self.submodules.counter1 = counter1 = Counter(bits_sign=8)
self.submodules.counter0 = counter0 = Counter(8)
self.submodules.counter1 = counter1 = Counter(8)
self.comb += [
counter0.ce.eq(1),
If(counter0.value == 16,