uniformize with litex cores and make things more clear about what LiteX vs Migen/MiSoC
This commit is contained in:
Florent Kermarrec
parent
aaf097056a
commit
64aa4ae4c0
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@ -1,5 +1,89 @@
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__pycache__
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*.pyc
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*.egg-info
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*.vcd
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outgoing
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# Byte-compiled / optimized / DLL files
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__pycache__/
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*.py[cod]
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*$py.class
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# C extensions
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*.so
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# Distribution / packaging
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.Python
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env/
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build/
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develop-eggs/
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dist/
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downloads/
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eggs/
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.eggs/
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lib/
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lib64/
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parts/
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sdist/
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var/
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*.egg-info/
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.installed.cfg
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*.egg
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# PyInstaller
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# Usually these files are written by a python script from a template
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# before PyInstaller builds the exe, so as to inject date/other infos into it.
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*.manifest
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*.spec
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# Installer logs
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pip-log.txt
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pip-delete-this-directory.txt
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# Unit test / coverage reports
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htmlcov/
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.tox/
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.coverage
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.coverage.*
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.cache
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nosetests.xml
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coverage.xml
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*,cover
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.hypothesis/
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# Translations
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*.mo
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*.pot
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# Django stuff:
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*.log
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local_settings.py
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# Flask stuff:
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instance/
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.webassets-cache
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# Scrapy stuff:
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.scrapy
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# Sphinx documentation
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docs/_build/
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# PyBuilder
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target/
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# IPython Notebook
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.ipynb_checkpoints
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# pyenv
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.python-version
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# celery beat schedule file
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celerybeat-schedule
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# dotenv
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.env
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# virtualenv
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venv/
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ENV/
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# Spyder project settings
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.spyderproject
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# Rope project settings
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.ropeproject
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39
README
39
README
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@ -5,29 +5,42 @@
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Migen inside
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Build your hardware, easily!
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Copyright 2012-2018 Enjoy-Digital
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Copyright 2012-2018 / EnjoyDigital
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[> Intro
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--------
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LiteX is an alternative to Migen/MiSoC maintained and used by Enjoy-Digital
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to build our cores, integrate them in complete SoC and load/flash them to
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the hardware and experiment new features.
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LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
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our cores, integrate them in complete SoC and load/flash them to the hardware
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and experiment new features.
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The structure of LiteX is kept close to Migen/MiSoC to ease collaboration
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between projects and efforts are made to keep cores developed with LiteX
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compatible with Migen/MiSoC.
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+---------------+
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|FPGA toolchains|
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+----^-----+----+
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| |
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+--+-----v--+
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+-------+ | |
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| Migen +--------> |
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+-------+ | | Your design
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| LiteX +---> ready to be used!
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| |
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+----------------------+ | |
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|LiteX Cores Ecosystem +--> |
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+----------------------+ +-^-------^-+
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(Eth,,SATA,,DRAM,,USB, | |
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PCIe,Video,etc...) + +
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board target
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file file
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[> License
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----------
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LiteX is Copyright (c) 2012-2017 Enjoy-Digital under BSD Lisense.
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Since it is based on Migen/MiSoC, please also refer to LICENSE file in gen/soc
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directory or git history to get correct copyrights.
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The structure of LiteX is kept close to MiSoC to ease collaboration between
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projects.
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[> Sub-packages
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---------------
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gen:
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Provides specific or experimental modules to generate HDL that are not integrated
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in Migen.
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in Migen. (For now a full copy of Migen is included in gen, aim is is to only
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keep specific or experimental modules)
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build:
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Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
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6
setup.py
6
setup.py
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@ -5,8 +5,8 @@ from setuptools import setup
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from setuptools import find_packages
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if sys.version_info[:3] < (3, 3):
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raise SystemExit("You need Python 3.3+")
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if sys.version_info[:3] < (3, 5):
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raise SystemExit("You need Python 3.5+")
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setup(
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@ -25,7 +25,7 @@ setup(
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classifiers=[
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"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
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"Environment :: Console",
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"Development Status :: Beta",
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"Development Status :: Alpha",
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"Intended Audience :: Developers",
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"License :: OSI Approved :: BSD License",
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"Operating System :: OS Independent",
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