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soc/integration/soc: Cleanup imports and directly use math.log2/ceil since math is already imported.

This commit is contained in:
Florent Kermarrec 2024-10-02 17:08:46 +02:00
parent 5e897752b7
commit 64cf925b39
1 changed files with 16 additions and 17 deletions
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15
litex/soc/integration/soc.py
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@ -13,7 +13,6 @@ import time
import logging import logging
import argparse import argparse
import datetime import datetime
from math import log2, ceil
from migen import * from migen import *
@ -93,8 +92,8 @@ class SoCRegion:
raise SoCError() raise SoCError()
if (not self.decode) or ((origin == 0) and (size == 2**bus.address_width)): if (not self.decode) or ((origin == 0) and (size == 2**bus.address_width)):
return lambda a: True return lambda a: True
origin >>= int(log2(bus.data_width//8)) # bytes to words aligned. origin >>= int(math.log2(bus.data_width//8)) # bytes to words aligned.
size >>= int(log2(bus.data_width//8)) # bytes to words aligned. size >>= int(math.log2(bus.data_width//8)) # bytes to words aligned.
return lambda a: (a[log2_int(size):] == (origin >> log2_int(size))) return lambda a: (a[log2_int(size):] == (origin >> log2_int(size)))
def __str__(self): def __str__(self):
@ -1681,7 +1680,7 @@ class LiteXSoC(SoC):
if hasattr(module, "_spd_data"): if hasattr(module, "_spd_data"):
# Pack the data into words of bus width. # Pack the data into words of bus width.
bytes_per_word = self.bus.data_width // 8 bytes_per_word = self.bus.data_width // 8
mem = [0] * ceil(len(module._spd_data) / bytes_per_word) mem = [0] * math.ceil(len(module._spd_data) / bytes_per_word)
for i in range(len(mem)): for i in range(len(mem)):
for offset in range(bytes_per_word): for offset in range(bytes_per_word):
mem[i] <<= 8 mem[i] <<= 8
@ -1733,7 +1732,7 @@ class LiteXSoC(SoC):
for mem_bus in self.cpu.memory_buses: for mem_bus in self.cpu.memory_buses:
# Request a LiteDRAM native port. # Request a LiteDRAM native port.
port = sdram.crossbar.get_port() port = sdram.crossbar.get_port()
port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2. port.data_width = 2**int(math.log2(port.data_width)) # Round to nearest power of 2.
# Check if bus is an AXI bus and connect it. # Check if bus is an AXI bus and connect it.
if isinstance(mem_bus, axi.AXIInterface): if isinstance(mem_bus, axi.AXIInterface):
@ -1804,7 +1803,7 @@ class LiteXSoC(SoC):
if connect_main_bus_to_dram: if connect_main_bus_to_dram:
# Request a LiteDRAM native port. # Request a LiteDRAM native port.
port = sdram.crossbar.get_port() port = sdram.crossbar.get_port()
port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2. port.data_width = 2**int(math.log2(port.data_width)) # Round to nearest power of 2.
# Create Wishbone Slave. # Create Wishbone Slave.
wb_sdram = wishbone.Interface(data_width=self.bus.data_width, address_width=32, addressing="word") wb_sdram = wishbone.Interface(data_width=self.bus.data_width, address_width=32, addressing="word")
@ -1814,7 +1813,7 @@ class LiteXSoC(SoC):
if l2_cache_size != 0: if l2_cache_size != 0:
# Insert L2 cache inbetween Wishbone bus and LiteDRAM # Insert L2 cache inbetween Wishbone bus and LiteDRAM
l2_cache_size = max(l2_cache_size, int(2*port.data_width/8)) # Use minimal size if lower l2_cache_size = max(l2_cache_size, int(2*port.data_width/8)) # Use minimal size if lower
l2_cache_size = 2**int(log2(l2_cache_size)) # Round to nearest power of 2 l2_cache_size = 2**int(math.log2(l2_cache_size)) # Round to nearest power of 2
l2_cache_data_width = max(port.data_width, l2_cache_min_data_width) l2_cache_data_width = max(port.data_width, l2_cache_min_data_width)
l2_cache = wishbone.Cache( l2_cache = wishbone.Cache(
cachesize = l2_cache_size//4, cachesize = l2_cache_size//4,
@ -2152,7 +2151,7 @@ class LiteXSoC(SoC):
if l2_cache_size != 0: if l2_cache_size != 0:
# Insert L2 cache inbetween Wishbone bus and LiteSPI # Insert L2 cache inbetween Wishbone bus and LiteSPI
l2_cache_size = max(l2_cache_size, int(2*32/8)) # Use minimal size if lower l2_cache_size = max(l2_cache_size, int(2*32/8)) # Use minimal size if lower
l2_cache_size = 2**int(log2(l2_cache_size)) # Round to nearest power of 2 l2_cache_size = 2**int(math.log2(l2_cache_size)) # Round to nearest power of 2
l2_cache = wishbone.Cache( l2_cache = wishbone.Cache(
cachesize = l2_cache_size//4, cachesize = l2_cache_size//4,
master = wb_spiram, master = wb_spiram,