Integrate with latest yosys changes
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@ -85,9 +85,9 @@ def _run_yosys(device, sources, vincpaths, build_name):
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for filename, language, library in sources:
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ys_contents += "read_{}{} {}\n".format(language, incflags, filename)
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ys_contents += """hierarchy -check -top top
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proc; memory; opt; fsm; opt
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synth_xilinx -top top -edif {build_name}.edif""".format(build_name=build_name)
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ys_contents += """hierarchy -top top
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synth_xilinx -top top -family xc6s -ise
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write_edif -pvector bra {build_name}.edif""".format(build_name=build_name)
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ys_name = build_name + ".ys"
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tools.write_to_file(ys_name, ys_contents)
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@ -114,7 +114,10 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
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settings = common.settings(ise_path, ver, "ISE_DS")
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build_script_contents += source_cmd + tools.cygpath(settings) + "\n"
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if mode == "edif":
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ext = "edif"
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ext = "ngo"
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build_script_contents += """
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edif2ngd {build_name}.edif {build_name}.{ext}{fail_stmt}
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"""
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else:
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ext = "ngc"
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build_script_contents += """
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@ -207,7 +210,8 @@ class XilinxISEToolchain:
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_build_xst_files(platform.device, platform.sources, platform.verilog_include_paths, build_name, self.xst_opt)
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isemode = mode
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else:
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_run_yosys(platform.device, platform.sources, platform.verilog_include_paths, build_name)
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if run:
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_run_yosys(platform.device, platform.sources, platform.verilog_include_paths, build_name)
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isemode = "edif"
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ngdbuild_opt += "-p " + platform.device
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