test: bit reverse
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@ -14,6 +14,7 @@ class ConstantCase(SimCase, unittest.TestCase):
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(Signal(3), Constant(-1, 7), 7),
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(Signal(3), Constant(0b10101)[:3], 0b101),
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(Signal(3), Constant(0b10101)[1:4], 0b10),
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(Signal(4), Constant(0b1100)[::-1], 0b0011),
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]
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self.comb += [a.eq(b) for a, b, c in self.sigs]
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