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soc_core: add back identifier

This commit is contained in:
Florent Kermarrec 2020-02-15 19:04:47 +01:00
parent 8f6114d0cd
commit 6576470179
2 changed files with 5 additions and 1 deletions
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2
litex/soc/integration/soc.py
View File

@ -881,7 +881,7 @@ class LiteXSoC(SoC):
self.check_if_exists(name)
if with_build_time:
identifier += " " + build_time()
setattr(self.submodules, name, Identifier(ident))
setattr(self.submodules, name, Identifier(identifier))
self.csr.add(name + "_mem", use_loc_if_exists=True)
# Add UART -------------------------------------------------------------------------------------

4
litex/soc/integration/soc_core.py
View File

@ -169,6 +169,10 @@ class SoCCore(LiteXSoC):
if integrated_main_ram_size:
self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size)
# Add Identifier
if ident != "":
self.add_identifier("identifier", identifier=ident, with_build_time=ident_version)
# Add UART
if with_uart:
self.add_uart(name=uart_name, baudrate=uart_baudrate)