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actorlib/spi/SingleGenerator: export CSRs
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commit
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1 changed files with 35 additions and 14 deletions
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@ -50,30 +50,51 @@ def _create_csrs_assign(layout, target, atomic, prefix=""):
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(MODE_EXTERNAL, MODE_SINGLE_SHOT, MODE_CONTINUOUS) = range(3)
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(MODE_EXTERNAL, MODE_SINGLE_SHOT, MODE_CONTINUOUS) = range(3)
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class SingleGenerator(Module):
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class SingleGenerator(Module, AutoCSR):
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def __init__(self, layout, mode):
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def __init__(self, layout, mode):
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self.source = Source(_convert_layout(layout))
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self.source = Source(_convert_layout(layout))
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self.busy = Signal()
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self.busy = Signal()
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self._csrs, assigns = _create_csrs_assign(layout, self.source.payload, mode != MODE_SINGLE_SHOT)
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self.comb += self.busy.eq(self.source.stb)
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if mode == MODE_EXTERNAL:
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if mode == MODE_EXTERNAL:
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self.trigger = Signal()
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self.trigger = Signal()
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trigger = self.trigger
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trigger = self.trigger
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elif mode == MODE_SINGLE_SHOT:
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elif mode == MODE_SINGLE_SHOT:
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shoot = CSR()
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self._r_shoot = CSR()
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self._csrs.insert(0, shoot)
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trigger = self._r_shoot.re
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trigger = shoot.re
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elif mode == MODE_CONTINUOUS:
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elif mode == MODE_CONTINUOUS:
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enable = CSRStorage()
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self._r_enable = CSRStorage()
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self._csrs.insert(0, enable)
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trigger = self._r_enable.storage
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trigger = enable.storage
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else:
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else:
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raise ValueError
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raise ValueError
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self.comb += self.busy.eq(self.source.stb)
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self.sync += If(self.source.ack | ~self.source.stb, self.source.stb.eq(trigger))
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stmts = [self.source.stb.eq(trigger)] + assigns
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self.sync += If(self.source.ack | ~self.source.stb, *stmts)
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self._create_csrs(layout, self.source.payload, mode != MODE_SINGLE_SHOT)
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def get_csrs(self):
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def _create_csrs(self, layout, target, atomic, prefix=""):
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return self._csrs
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for element in layout:
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if isinstance(element[1], list):
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self._create_csrs(element[1], atomic,
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getattr(target, element[0]),
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element[0] + "_")
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else:
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name = element[0]
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nbits = element[1]
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if len(element) > 2:
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reset = element[2]
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else:
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reset = 0
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if len(element) > 3:
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alignment = element[3]
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else:
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alignment = 0
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regname = prefix + name
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reg = CSRStorage(nbits + alignment, reset=reset, atomic_write=atomic,
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alignment_bits=alignment, name=regname)
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setattr(self, "r_"+regname, reg)
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self.sync += If(self.source.ack | ~self.source.stb,
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getattr(target, name).eq(reg.storage))
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class Collector(Module, AutoCSR):
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class Collector(Module, AutoCSR):
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def __init__(self, layout, depth=1024):
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def __init__(self, layout, depth=1024):
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