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integration/soc/add_sdram: add with_bist parameter to add LiteDRAM's BIST. 

sdram_bist command will then be available in the BIOS:

litex> sdram_bist
sdram_bist <burst_length> <random>
litex> sdram_bist 256 0
Starting SDRAM BIST with burst_length=256 and random=0
WR-SPEED(MiB/s) RD-SPEED(MiB/s)  TESTED(MiB)       ERRORS
            473             455            0            0
            473             455           25            0
            473             455           50            0
            473             455           75            0
            473             455          100            0
            473             455          125            0
            473             455          150            0
            473             455          175            0
            473             455          200            0
            473             455          225            0
WR-SPEED(MiB/s) RD-SPEED(MiB/s)  TESTED(MiB)       ERRORS
            473             455          250            0
            473             455          275            0
            473             455          300            0
            473             455          325            0
            473             455          350            0
            473             455          375            0
            473             455          400            0
            473             455          425            0
            473             455          450            0
            473             455          475            0
WR-SPEED(MiB/s) RD-SPEED(MiB/s)  TESTED(MiB)       ERRORS
            473             455          500            0
            473             455          525            0
            473             455          550            0
            473             455          575            0
            473             455          600            0
            473             455          625            0

litex>
This commit is contained in:
Florent Kermarrec 2020-11-05 13:41:37 +01:00
parent 97b35a0771
commit 65f19b5c4a
1 changed files with 10 additions and 1 deletions
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11
litex/soc/integration/soc.py
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@ -1141,7 +1141,7 @@ class LiteXSoC(SoC):
self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
# Add SDRAM ------------------------------------------------------------------------------------
def add_sdram(self, name, phy, module, origin, size=None, with_soc_interconnect=True,
def add_sdram(self, name, phy, module, origin, size=None, with_bist=False, with_soc_interconnect=True,
l2_cache_size = 8192,
l2_cache_min_data_width = 128,
l2_cache_reverse = True,
@ -1153,6 +1153,7 @@ class LiteXSoC(SoC):
from litedram.core import LiteDRAMCore
from litedram.frontend.wishbone import LiteDRAMWishbone2Native
from litedram.frontend.axi import LiteDRAMAXI2Native
from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker
# LiteDRAM core
self.submodules.sdram = LiteDRAMCore(
@ -1183,6 +1184,13 @@ class LiteXSoC(SoC):
contents = mem,
)
# LiteDRAM BIST
if with_bist:
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.add_csr("sdram_generator")
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
self.add_csr("sdram_checker")
if not with_soc_interconnect: return
# Compute/Check SDRAM size
@ -1294,6 +1302,7 @@ class LiteXSoC(SoC):
port = port,
base_address = self.bus.regions["main_ram"].origin)
# Add Ethernet ---------------------------------------------------------------------------------
def add_ethernet(self, name="ethmac", phy=None):
# Imports