lite*: adapt to new ModuleTransformer semantics

NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
This commit is contained in:
Robert Jordens 2015-04-02 14:28:42 -06:00 committed by Sebastien Bourdeauducq
parent 2583e975f0
commit 66f8dcbfaf
4 changed files with 12 additions and 11 deletions

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@ -2,7 +2,6 @@ import math
from collections import OrderedDict
from migen.fhdl.std import *
from migen.fhdl.decorators import ModuleDecorator
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.record import *
from migen.genlib.fsm import FSM, NextState

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@ -1,3 +1,4 @@
from migen.fhdl.decorators import ModuleTransformer
from misoclib.com.liteeth.common import *
# Generic classes
@ -10,15 +11,16 @@ class Port:
return r
# Generic modules
class BufferizeEndpoints(ModuleDecorator):
def __init__(self, submodule, *args):
ModuleDecorator.__init__(self, submodule)
class BufferizeEndpoints(ModuleTransformer):
def __init__(self, *names):
self.names = names
def transform_instance(self, submodule):
endpoints = get_endpoints(submodule)
sinks = {}
sources = {}
for name, endpoint in endpoints.items():
if name in args or len(args) == 0:
if not self.names or name in self.names:
if isinstance(endpoint, Sink):
sinks.update({name : endpoint})
elif isinstance(endpoint, Source):

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@ -1,7 +1,7 @@
import math
from migen.fhdl.std import *
from migen.fhdl.decorators import ModuleDecorator
from migen.fhdl.decorators import ModuleTransformer
from migen.genlib.resetsync import *
from migen.genlib.fsm import *
from migen.genlib.record import *
@ -252,15 +252,16 @@ def sectors2dwords(n):
return n*logical_sector_size//4
# Generic modules
class BufferizeEndpoints(ModuleDecorator):
def __init__(self, submodule, *args):
ModuleDecorator.__init__(self, submodule)
class BufferizeEndpoints(ModuleTransformer):
def __init__(self, *names):
self.names = names
def transform_instance(self, submodule):
endpoints = get_endpoints(submodule)
sinks = {}
sources = {}
for name, endpoint in endpoints.items():
if name in args or len(args) == 0:
if not self.names or name in self.names:
if isinstance(endpoint, Sink):
sinks.update({name : endpoint})
elif isinstance(endpoint, Source):

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@ -1,7 +1,6 @@
from misoclib.mem.litesata.common import *
from misoclib.mem.litesata.core.link.scrambler import Scrambler
from migen.fhdl.decorators import ModuleDecorator
from migen.bank.description import *
class LiteSATABISTGenerator(Module):