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replace flen with len

This commit is contained in:
Sebastien Bourdeauducq 2015-09-26 18:50:11 +08:00
parent da425d1bcb
commit 67133f3542
13 changed files with 44 additions and 44 deletions
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8
misoc/cores/dfii.py
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@ -8,10 +8,10 @@ class PhaseInjector(Module, AutoCSR):
def __init__(self, phase):
self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
self._command_issue = CSR()
self._address = CSRStorage(flen(phase.address))
self._baddress = CSRStorage(flen(phase.bank))
self._wrdata = CSRStorage(flen(phase.wrdata))
self._rddata = CSRStatus(flen(phase.rddata))
self._address = CSRStorage(len(phase.address))
self._baddress = CSRStorage(len(phase.bank))
self._wrdata = CSRStorage(len(phase.wrdata))
self._rddata = CSRStatus(len(phase.rddata))
###

4
misoc/cores/gpio.py
View File

@ -5,13 +5,13 @@ from migen.bank.description import *
class GPIOIn(Module, AutoCSR):
def __init__(self, signal):
self._in = CSRStatus(flen(signal))
self._in = CSRStatus(len(signal))
self.specials += MultiReg(signal, self._in.status)
class GPIOOut(Module, AutoCSR):
def __init__(self, signal):
self._out = CSRStorage(flen(signal))
self._out = CSRStorage(len(signal))
self.comb += signal.eq(self._out.storage)

2
misoc/cores/lasmicon/bankmachine.py
View File

@ -35,7 +35,7 @@ class BankMachine(Module):
###
# Request FIFO
self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))],
self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", len(req.adr))],
controller_settings.req_queue_size)
self.comb += [
self.req_fifo.din.we.eq(req.we),

2
misoc/cores/lasmicon/multiplexer.py
View File

@ -34,7 +34,7 @@ class _CommandChooser(Module):
self.want_writes = Signal()
self.want_cmds = Signal()
# NB: cas_n/ras_n/we_n are 1 when stb is inactive
self.cmd = CommandRequestRW(flen(requests[0].a), flen(requests[0].ba))
self.cmd = CommandRequestRW(len(requests[0].a), len(requests[0].ba))
###

4
misoc/cores/liteeth_mini/mac/core/crc.py
View File

@ -138,7 +138,7 @@ class LiteEthMACCRCInserter(Module):
# # #
dw = flen(sink.data)
dw = len(sink.data)
crc = crc_class(dw)
fsm = FSM(reset_state="IDLE")
self.submodules += crc, fsm
@ -219,7 +219,7 @@ class LiteEthMACCRCChecker(Module):
# # #
dw = flen(sink.data)
dw = len(sink.data)
crc = crc_class(dw)
self.submodules += crc
ratio = crc.width//dw

4
misoc/cores/liteeth_mini/phy/__init__.py
View File

@ -7,7 +7,7 @@ def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
# This is a simulation PHY
from misoc.com.liteethmini.phy.sim import LiteEthPHYSim
return LiteEthPHYSim(pads)
elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8:
elif hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8:
if hasattr(clock_pads, "tx"):
# This is a 10/100/1G PHY
from misoc.com.liteethmini.phy.gmii_mii import LiteEthPHYGMIIMII
@ -19,7 +19,7 @@ def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
elif hasattr(pads, "rx_ctl"):
# This is a 10/100/1G RGMII PHY
raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
elif flen(pads.tx_data) == 4:
elif len(pads.tx_data) == 4:
# This is a MII PHY
from misoc.com.liteethmini.phy.mii import LiteEthPHYMII
return LiteEthPHYMII(clock_pads, pads, **kwargs)

2
misoc/cores/minicon/test.py
View File

@ -32,7 +32,7 @@ class MiniconTB(Module):
self.submodules.slave = Minicon(phy_settings, sdram_geom, sdram_timing)
self.submodules.tap = wishbone.Tap(self.slave.bus)
self.submodules.dc = dc = wishbone.DownConverter(32, phy_settings.nphases*flen(dfi.phases[rdphase].rddata))
self.submodules.dc = dc = wishbone.DownConverter(32, phy_settings.nphases*len(dfi.phases[rdphase].rddata))
self.submodules.master = wishbone.Initiator(self.genxfers(), bus=dc.wishbone_i)
self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, self.slave.bus)

6
misoc/cores/sdram_phy/gensdrphy.py
View File

@ -30,9 +30,9 @@ from misoc.cores import sdram_settings
class GENSDRPHY(Module):
def __init__(self, pads, module):
addressbits = flen(pads.a)
bankbits = flen(pads.ba)
databits = flen(pads.dq)
addressbits = len(pads.a)
bankbits = len(pads.ba)
databits = len(pads.dq)
self.settings = sdram_settings.PhySettings(
memtype=module.memtype,

6
misoc/cores/sdram_phy/k7ddrphy.py
View File

@ -9,9 +9,9 @@ from misoc.cores import sdram_settings
class K7DDRPHY(Module, AutoCSR):
def __init__(self, pads, module):
addressbits = flen(pads.a)
bankbits = flen(pads.ba)
databits = flen(pads.dq)
addressbits = len(pads.a)
bankbits = len(pads.ba)
databits = len(pads.dq)
nphases = 4
self._wlevel_en = CSRStorage()

12
misoc/cores/sdram_phy/s6ddrphy.py
View File

@ -30,9 +30,9 @@ class S6HalfRateDDRPHY(Module):
def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
if module.memtype not in ["DDR", "LPDDR", "DDR2", "DDR3"]:
raise NotImplementedError("S6HalfRateDDRPHY only supports DDR, LPDDR, DDR2 and DDR3")
addressbits = flen(pads.a)
bankbits = flen(pads.ba)
databits = flen(pads.dq)
addressbits = len(pads.a)
bankbits = len(pads.ba)
databits = len(pads.dq)
nphases = 2
if module.memtype == "DDR3":
@ -405,9 +405,9 @@ class S6QuarterRateDDRPHY(Module):
half_rate_phy = S6HalfRateDDRPHY(pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment)
self.submodules += RenameClockDomains(half_rate_phy, {"sys" : "sys2x"})
addressbits = flen(pads.a)
bankbits = flen(pads.ba)
databits = flen(pads.dq)
addressbits = len(pads.a)
bankbits = len(pads.ba)
databits = len(pads.dq)
nphases = 4
self.settings = sdram_settings.PhySettings(

4
misoc/cores/spi_flash.py
View File

@ -35,7 +35,7 @@ class SpiFlash(Module, AutoCSR):
Optionally supports software bitbanging (for write, erase, or other commands).
"""
self.bus = bus = wishbone.Interface()
spi_width = flen(pads.dq)
spi_width = len(pads.dq)
if with_bitbang:
self.bitbang = CSRStorage(4)
self.miso = CSRStatus()
@ -46,7 +46,7 @@ class SpiFlash(Module, AutoCSR):
cs_n = Signal(reset=1)
clk = Signal()
dq_oe = Signal()
wbone_width = flen(bus.dat_r)
wbone_width = len(bus.dat_r)
read_cmd_params = {

8
misoc/interconnect/csr_bus.py
View File

@ -31,7 +31,7 @@ class SRAM(Module):
if bus is None:
bus = Interface()
self.bus = bus
data_width = flen(self.bus.dat_w)
data_width = len(self.bus.dat_w)
if isinstance(mem_or_size, Memory):
mem = mem_or_size
else:
@ -89,10 +89,10 @@ class SRAM(Module):
]
if self._page is None:
self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+flen(port.adr)])
self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+len(port.adr)])
else:
pv = self._page.storage
self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+flen(port.adr)-flen(pv)], pv))
self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+len(port.adr)-len(pv)], pv))
def get_csrs(self):
if self._page is None:
@ -109,7 +109,7 @@ class CSRBank(csr.GenericBank):
###
csr.GenericBank.__init__(self, description, flen(self.bus.dat_w))
csr.GenericBank.__init__(self, description, len(self.bus.dat_w))
sel = Signal()
self.comb += sel.eq(self.bus.adr[9:] == address)

26
misoc/interconnect/wishbone.py
View File

@ -102,7 +102,7 @@ class Decoder(Module):
]
# mux (1-hot) slave data return
masked = [Replicate(slave_sel_r[i], flen(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
masked = [Replicate(slave_sel_r[i], len(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
self.comb += master.dat_r.eq(reduce(or_, masked))
@ -144,8 +144,8 @@ class DownConverter(Module):
Manage err signal? (Not implemented since we generally don't use it on Migen/MiSoC modules)
"""
def __init__(self, master, slave):
dw_from = flen(master.dat_r)
dw_to = flen(slave.dat_w)
dw_from = len(master.dat_r)
dw_to = len(slave.dat_w)
ratio = dw_from//dw_to
# # #
@ -251,8 +251,8 @@ class UpConverter(Module):
Manage err signal? (Not implemented since we generally don't use it on Migen/MiSoC modules)
"""
def __init__(self, master, slave):
dw_from = flen(master.dat_r)
dw_to = flen(slave.dat_w)
dw_from = len(master.dat_r)
dw_to = len(slave.dat_w)
ratio = dw_to//dw_from
ratiobits = log2_int(ratio)
@ -402,8 +402,8 @@ class Converter(Module):
# # #
dw_from = flen(master.dat_r)
dw_to = flen(slave.dat_r)
dw_from = len(master.dat_r)
dw_to = len(slave.dat_r)
if dw_from > dw_to:
downconverter = DownConverter(master, slave)
self.submodules += downconverter
@ -426,8 +426,8 @@ class Cache(Module):
###
dw_from = flen(master.dat_r)
dw_to = flen(slave.dat_r)
dw_from = len(master.dat_r)
dw_to = len(slave.dat_r)
if dw_to > dw_from and (dw_to % dw_from) != 0:
raise ValueError("Slave data width must be a multiple of {dw}".format(dw=dw_from))
if dw_to < dw_from and (dw_from % dw_to) != 0:
@ -436,7 +436,7 @@ class Cache(Module):
# Split address:
# TAG | LINE NUMBER | LINE OFFSET
offsetbits = log2_int(max(dw_to//dw_from, 1))
addressbits = flen(slave.adr) + offsetbits
addressbits = len(slave.adr) + offsetbits
linebits = log2_int(cachesize) - offsetbits
tagbits = addressbits - linebits
wordbits = log2_int(max(dw_from//dw_to, 1))
@ -574,7 +574,7 @@ class SRAM(Module):
if bus is None:
bus = Interface()
self.bus = bus
bus_data_width = flen(self.bus.dat_r)
bus_data_width = len(self.bus.dat_r)
if isinstance(mem_or_size, Memory):
assert(mem_or_size.width <= bus_data_width)
self.mem = mem_or_size
@ -597,7 +597,7 @@ class SRAM(Module):
for i in range(4)]
# address and data
self.comb += [
port.adr.eq(self.bus.adr[:flen(port.adr)]),
port.adr.eq(self.bus.adr[:len(port.adr)]),
self.bus.dat_r.eq(port.dat_r)
]
if not read_only:
@ -617,7 +617,7 @@ class CSRBank(csr.GenericBank):
###
GenericBank.__init__(self, description, flen(self.bus.dat_w))
GenericBank.__init__(self, description, len(self.bus.dat_w))
for i, c in enumerate(self.simple_csrs):
self.comb += [