cores/hyperbus: Update docstring.

This commit is contained in:
Florent Kermarrec 2024-04-15 15:05:58 +02:00
parent d25fd85f55
commit 67586e8a24
1 changed files with 16 additions and 5 deletions

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@ -24,12 +24,23 @@ class HyperRAM(LiteXModule):
tCSM = 4e-6
Provides a very simple/minimal HyperRAM core that should work with all FPGA/HyperRam chips:
- FPGA vendor agnostic.
- no setup/chip configuration (use default latency).
Provides a very simple/minimal HyperRAM core with a Wishbone Interface that can work with all
FPGA/HyperRam chips:
- Vendor agnostic.
- Fixed/Variable latency.
- Latency/Registers (re-)configuration.
This core favors portability and ease of use over performance.
pads (Record) : Interface to the HyperRAM connection pads.
latency (int, optional) : Initial latency setting, defaults to 6.
latency_mode (str, optional) : Specifies the latency mode ('fixed' or 'variable'), defaults to 'fixed'.
sys_clk_freq (float, optional) : System clock frequency in Hz.
with_csr (bool, optional) : Enables CSR interface for Latency/Registers configuration, defaults to True.
pads (Record) : Platform pads of HyperRAM.
bus (wishbone.Interface) : Wishbone Interface.
def __init__(self, pads, latency=6, latency_mode="fixed", sys_clk_freq=None, with_csr=True):
self.pads = pads
self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")