mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
improve BIST and clean up (remove support of identify command and debug code)
This commit is contained in:
Florent Kermarrec
parent
38d3f3697b
commit
678ee33af4
14 changed files with 176 additions and 448 deletions
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@ -5,6 +5,11 @@ from lib.sata.command import SATACommand
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class SATACON(Module):
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def __init__(self, phy, sector_size=512, max_count=8):
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self.sector_size = sector_size
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self.max_count = max_count
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###
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self.link = SATALink(phy)
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self.transport = SATATransport(self.link)
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self.command = SATACommand(self.transport, sector_size=sector_size, max_count=max_count)
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@ -1,10 +1,11 @@
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from lib.sata.common import *
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from lib.sata.link.scrambler import Scrambler
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from migen.bank.description import *
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class SATABIST(Module):
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def __init__(self, sector_size=512):
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self.sink = sink = Sink(command_rx_description(32))
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self.source = source = Source(command_tx_description(32))
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class SATABISTUnit(Module):
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def __init__(self, sata_con):
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sink = sata_con.source
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source = sata_con.sink
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self.start = Signal()
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self.sector = Signal(48)
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@ -36,7 +37,7 @@ class SATABIST(Module):
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fsm.act("SEND_WRITE_CMD_AND_DATA",
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source.stb.eq(1),
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source.sop.eq((counter.value == 0)),
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source.eop.eq((counter.value == (sector_size//4*self.count)-1)),
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source.eop.eq((counter.value == (sata_con.sector_size//4*self.count)-1)),
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source.write.eq(1),
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source.sector.eq(self.sector),
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source.count.eq(self.count),
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@ -87,3 +88,65 @@ class SATABIST(Module):
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)
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)
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)
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class SATABIST(Module, AutoCSR):
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def __init__(self, sata_con):
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self._start = CSR()
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self._start_sector = CSRStorage(48)
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self._count = CSRStorage(4)
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self._stop = CSRStorage()
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self._sector = CSRStatus(48)
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self._errors = CSRStatus(32)
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start = self._start.r & self._start.re
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start_sector = self._start_sector.storage
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count = self._count.storage
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stop = self._stop.storage
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update = Signal()
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sector = self._sector.status
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errors = self._errors.status
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###
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self.unit = SATABISTUnit(sata_con)
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self.comb += [
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self.unit.sector.eq(sector),
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self.unit.count.eq(count)
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]
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self.fsm = fsm = FSM(reset_state="IDLE")
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# FSM
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fsm.act("IDLE",
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If(start,
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NextState("START")
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)
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)
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fsm.act("START",
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self.unit.start.eq(1),
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NextState("WAIT_DONE")
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)
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fsm.act("WAIT_DONE",
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If(self.unit.done,
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NextState("CHECK_PREPARE")
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).Elif(stop,
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NextState("IDLE")
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)
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)
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fsm.act("CHECK_PREPARE",
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update.eq(1),
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NextState("START")
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)
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self.sync += [
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If(start,
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errors.eq(0),
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sector.eq(start_sector)
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).Elif(update,
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errors.eq(errors + self.unit.data_errors),
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sector.eq(sector + count)
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)
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]
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@ -3,7 +3,6 @@ from lib.sata.common import *
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tx_to_rx = [
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("write", 1),
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("read", 1),
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("identify", 1),
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("count", 4)
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]
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@ -39,8 +38,6 @@ class SATACommandTX(Module):
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NextState("SEND_WRITE_DMA_CMD")
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).Elif(sink.read,
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NextState("SEND_READ_DMA_CMD")
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).Elif(sink.identify,
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NextState("SEND_IDENTIFY_CMD")
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).Else(
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sink.ack.eq(1)
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)
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@ -87,24 +84,11 @@ class SATACommandTX(Module):
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NextState("IDLE")
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)
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)
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fsm.act("SEND_IDENTIFY_CMD",
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(1),
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transport.sink.eop.eq(1),
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transport.sink.type.eq(fis_types["REG_H2D"]),
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transport.sink.c.eq(1),
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transport.sink.command.eq(regs["IDENTIFY_DEVICE_DMA"]),
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sink.ack.eq(transport.sink.ack),
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If(sink.stb & sink.ack,
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NextState("IDLE")
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)
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)
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self.comb += [
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If(sink.stb,
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to_rx.write.eq(sink.write),
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to_rx.read.eq(sink.read),
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to_rx.identify.eq(sink.identify),
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to_rx.count.eq(sink.count)
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)
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]
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@ -131,15 +115,10 @@ class SATACommandRX(Module):
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transport.source.ack.eq(1),
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If(from_tx.write,
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NextState("WAIT_WRITE_ACTIVATE")
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).Elif(from_tx.read | from_tx.identify,
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).Elif(from_tx.read,
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NextState("WAIT_READ_DATA")
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)
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)
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identify = Signal()
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self.sync += \
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If(fsm.ongoing("IDLE"),
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identify.eq(from_tx.identify)
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)
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fsm.act("WAIT_WRITE_ACTIVATE",
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transport.source.ack.eq(1),
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If(transport.source.stb,
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@ -202,11 +181,10 @@ class SATACommandRX(Module):
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)
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fsm.act("PRESENT_READ_RESPONSE",
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cmd_fifo.sink.stb.eq(1),
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cmd_fifo.sink.read.eq(~identify),
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cmd_fifo.sink.identify.eq(identify),
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cmd_fifo.sink.read.eq(1),
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cmd_fifo.sink.success.eq(1),
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cmd_fifo.sink.failed.eq(0),
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If(~cmd_fifo.fifo.readable, # Note: simulate a depth=1 fifo
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If(~cmd_fifo.fifo.readable, # Note: simulate a fifo with depth=1
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If(cmd_fifo.sink.stb & cmd_fifo.sink.ack,
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If(cmd_fifo.sink.failed,
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data_fifo.reset.eq(1)
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@ -220,7 +198,7 @@ class SATACommandRX(Module):
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out_fsm.act("IDLE",
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If(cmd_fifo.source.stb & cmd_fifo.source.write,
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NextState("PRESENT_WRITE_RESPONSE"),
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).Elif(cmd_fifo.source.stb & (cmd_fifo.source.read | cmd_fifo.source.identify),
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).Elif(cmd_fifo.source.stb & (cmd_fifo.source.read),
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If(cmd_fifo.source.success,
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NextState("PRESENT_READ_RESPONSE_SUCCESS"),
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).Else(
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@ -242,7 +220,6 @@ class SATACommandRX(Module):
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out_fsm.act("PRESENT_READ_RESPONSE_SUCCESS",
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source.stb.eq(data_fifo.source.stb),
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source.read.eq(cmd_fifo.source.read),
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source.identify.eq(cmd_fifo.source.identify),
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source.success.eq(1),
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source.sop.eq(data_fifo.source.sop),
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source.eop.eq(data_fifo.source.eop),
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@ -258,7 +235,6 @@ class SATACommandRX(Module):
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source.sop.eq(1),
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source.eop.eq(1),
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source.read.eq(cmd_fifo.source.read),
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source.identify.eq(cmd_fifo.source.identify),
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source.failed.eq(1),
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If(source.stb & source.ack,
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cmd_fifo.source.ack.eq(1),
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@ -143,15 +143,13 @@ def transport_rx_description(dw):
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# Command Layer
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regs = {
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"WRITE_DMA_EXT" : 0x35,
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"READ_DMA_EXT" : 0x25,
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"IDENTIFY_DEVICE_DMA" : 0xEE
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"READ_DMA_EXT" : 0x25
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}
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def command_tx_description(dw):
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layout = [
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("write", 1),
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("read", 1),
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("identify", 1),
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("sector", 48),
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("count", 4),
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("data", dw)
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@ -162,7 +160,6 @@ def command_rx_description(dw):
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layout = [
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("write", 1),
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("read", 1),
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("identify", 1),
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("success", 1),
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("failed", 1),
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("data", dw)
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@ -173,7 +170,6 @@ def command_rx_cmd_description(dw):
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layout = [
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("write", 1),
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("read", 1),
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("identify", 1),
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("success", 1),
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("failed", 1)
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]
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@ -10,7 +10,7 @@ from_rx = [
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]
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class SATALinkTX(Module):
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def __init__(self, phy, disable_cont=False):
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def __init__(self, phy):
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self.sink = Sink(link_description(32))
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self.from_rx = Sink(from_rx)
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@ -34,7 +34,7 @@ class SATALinkTX(Module):
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# inserter CONT and scrambled data between
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# CONT and next primitive
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self.cont = cont = SATACONTInserter(phy_description(32), disable=False)
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self.cont = cont = SATACONTInserter(phy_description(32))
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# datas / primitives mux
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insert = Signal(32)
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@ -200,7 +200,7 @@ class SATALinkRX(Module):
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)
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)
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fsm.act("WTRM",
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# XXX: check CRC resutlt to return R_ERR or R_OK
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# XXX: check CRC result to return R_ERR or R_OK
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insert.eq(primitives["R_OK"]),
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If(det == primitives["SYNC"],
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NextState("IDLE")
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@ -215,8 +215,8 @@ class SATALinkRX(Module):
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]
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class SATALink(Module):
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def __init__(self, phy, disable_tx_cont=False):
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self.tx = SATALinkTX(phy, disable_tx_cont)
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def __init__(self, phy):
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self.tx = SATALinkTX(phy)
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self.rx = SATALinkRX(phy)
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self.comb += Record.connect(self.rx.to_tx, self.tx.from_rx)
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self.sink, self.source = self.tx.sink, self.rx.source
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@ -4,15 +4,12 @@ from lib.sata.link.scrambler import Scrambler
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from migen.genlib.misc import optree
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class SATACONTInserter(Module):
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def __init__(self, description, disable=False):
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def __init__(self, description):
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self.sink = sink = Sink(description)
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self.source = source = Source(description)
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###
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if disable:
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self.comb += Record.connect(self.sink, self.source)
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else:
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self.counter = counter = Counter(max=4)
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is_data = Signal()
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@ -7,12 +7,11 @@ from lib.sata.test.hdd import *
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from lib.sata.test.common import *
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class CommandTXPacket(list):
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def __init__(self, write=0, read=0, identify=0, sector=0, count=0, data=[]):
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def __init__(self, write=0, read=0, sector=0, count=0, data=[]):
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self.ongoing = False
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self.done = False
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self.write = write
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self.read = read
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self.identify = identify
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self.sector = sector
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self.count = count
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for d in data:
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@ -26,7 +25,6 @@ class CommandStreamer(PacketStreamer):
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PacketStreamer.do_simulation(self, selfp)
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selfp.source.write = self.packet.write
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selfp.source.read = self.packet.read
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selfp.source.identify = self.packet.identify
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selfp.source.sector = self.packet.sector
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selfp.source.count = self.packet.count
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@ -36,7 +34,6 @@ class CommandRXPacket(list):
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self.done = False
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self.write = 0
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self.read = 0
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self.identify = 0
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self.success = 0
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self.failed = 0
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@ -50,7 +47,6 @@ class CommandLogger(PacketLogger):
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self.packet = CommandRXPacket()
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self.packet.write = selfp.sink.write
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self.packet.read = selfp.sink.read
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self.packet.identify = selfp.sink.identify
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self.packet.sucess = selfp.sink.success
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self.packet.failed = selfp.sink.failed
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self.packet.append(selfp.sink.data)
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@ -100,8 +96,5 @@ class TB(Module):
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s, l, e = check(write_data, read_data)
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print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
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identify_packet = CommandTXPacket(identify=1)
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yield from self.streamer.send(identify_packet)
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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@ -421,8 +421,6 @@ class CommandLayer(Module):
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resp = self.hdd.write_dma_callback(fis)
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elif fis.command == regs["READ_DMA_EXT"]:
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resp = self.hdd.read_dma_callback(fis)
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elif fis.command == regs["IDENTIFY_DEVICE_DMA"]:
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resp = self.hdd.identify_device_dma_callback(fis)
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elif isinstance(fis, FIS_DATA):
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resp = self.hdd.data_callback(fis)
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@ -508,12 +506,6 @@ class HDD(Module):
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packet.insert(0, 0)
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return [FIS_DATA(packet, direction="D2H"), FIS_REG_D2H()]
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def identify_device_dma_callback(self, fis):
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print_hdd("Identify device request")
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packet = [i for i in range(256)]
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packet.insert(0, 0)
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return [FIS_DATA(packet, direction="D2H"), FIS_REG_D2H()]
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def data_callback(self, fis):
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self.write(self.wr_sector, fis.packet[1:])
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self.wr_sector += self.dwords2sectors(len(fis.packet[1:]))
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178
targets/test.py
178
targets/test.py
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@ -152,179 +152,6 @@ class ClockLeds(Module):
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sata_tx_cnt.eq(sata_tx_cnt-1)
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)
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class CommandGenerator(Module, AutoCSR):
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def __init__(self, sata_con, sector_size):
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self._write = CSR()
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self._read = CSR()
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self._identify = CSR()
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self._sector = CSRStorage(48)
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self._count = CSRStorage(4)
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self._data = CSRStorage(32) # Note: fixed data, add a fifo later
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self._sucess = CSRStatus()
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self._failed = CSRStatus()
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self.fsm = fsm = FSM(reset_state="IDLE")
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def new_command(csr):
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return csr.r & csr.re
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cnt = Signal(16)
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sector = self._sector.storage
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count = self._count.storage
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data = self._data.storage
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success = self._sucess.status
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failed = self._failed.status
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clr_status = Signal()
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set_success = Signal()
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set_failed = Signal()
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self.sync += [
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If(clr_status,
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success.eq(0),
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failed.eq(0),
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).Elif(set_success,
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success.eq(1)
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).Elif(set_failed,
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failed.eq(1)
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)
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]
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self.comb += sata_con.source.ack.eq(1)
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# FSM
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fsm.act("IDLE",
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clr_status.eq(1),
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If(new_command(self._write),
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NextState("SEND_WRITE_CMD")
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).Elif(new_command(self._read),
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NextState("SEND_READ_CMD")
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).Elif(new_command(self._identify),
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NextState("SEND_IDENTIFY_CMD")
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)
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)
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fsm.act("SEND_WRITE_CMD",
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sata_con.sink.stb.eq(1),
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sata_con.sink.sop.eq(cnt == 0),
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sata_con.sink.eop.eq(cnt == (count*sector_size-1)),
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sata_con.sink.write.eq(1),
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sata_con.sink.sector.eq(sector),
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sata_con.sink.count.eq(count),
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sata_con.sink.data.eq(data),
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If(sata_con.sink.eop & sata_con.sink.ack,
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NextState("WAIT_WRITE_ACK")
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)
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)
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self.sync += [
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If(fsm.ongoing("IDLE"),
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cnt.eq(0)
|
||||
).Elif(sata_con.sink.stb & sata_con.sink.stb,
|
||||
cnt.eq(cnt+1)
|
||||
)
|
||||
]
|
||||
fsm.act("WAIT_WRITE_ACK",
|
||||
# XXX: add check of success / failed
|
||||
If(sata_con.source.stb & sata_con.source.eop,
|
||||
set_success.eq(1),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("SEND_READ_CMD",
|
||||
sata_con.sink.stb.eq(1),
|
||||
sata_con.sink.sop.eq(1),
|
||||
sata_con.sink.eop.eq(1),
|
||||
sata_con.sink.read.eq(1),
|
||||
sata_con.sink.sector.eq(sector),
|
||||
sata_con.sink.count.eq(count),
|
||||
If(sata_con.sink.ack,
|
||||
NextState("WAIT_READ_ACK_AND_DATA")
|
||||
)
|
||||
)
|
||||
fsm.act("WAIT_READ_ACK_AND_DATA",
|
||||
# XXX: add check of success / failed and receive data
|
||||
If(sata_con.source.stb & sata_con.source.eop,
|
||||
set_success.eq(1),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("SEND_IDENTIFY_CMD",
|
||||
sata_con.sink.stb.eq(1),
|
||||
sata_con.sink.sop.eq(1),
|
||||
sata_con.sink.eop.eq(1),
|
||||
sata_con.sink.identify.eq(1),
|
||||
If(sata_con.sink.ack,
|
||||
NextState("WAIT_IDENTIFY_ACK_AND_DATA")
|
||||
)
|
||||
)
|
||||
fsm.act("WAIT_IDENTIFY_ACK_AND_DATA",
|
||||
# XXX: add check of success / failed and receive data
|
||||
If(sata_con.source.stb & sata_con.source.eop,
|
||||
set_success.eq(1),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
class BIST(Module, AutoCSR):
|
||||
def __init__(self, sata_con, sector_size):
|
||||
self._start = CSR()
|
||||
self._stop = CSR()
|
||||
|
||||
self._sector = CSRStatus(48)
|
||||
self._ctrl_errors = CSRStatus(32)
|
||||
self._data_errors = CSRStatus(32)
|
||||
|
||||
check_prepare = Signal()
|
||||
sector = self._sector.status
|
||||
ctrl_errors = self._ctrl_errors.status
|
||||
data_errors = self._data_errors.status
|
||||
|
||||
###
|
||||
|
||||
self.sata_bist = SATABIST(sector_size)
|
||||
self.comb += [
|
||||
Record.connect(sata_con.source, self.sata_bist.sink),
|
||||
Record.connect(self.sata_bist.source, sata_con.sink)
|
||||
]
|
||||
|
||||
self.fsm = fsm = FSM(reset_state="IDLE")
|
||||
|
||||
self.comb += [
|
||||
self.sata_bist.sector.eq(sector),
|
||||
self.sata_bist.count.eq(4)
|
||||
]
|
||||
|
||||
# FSM
|
||||
fsm.act("IDLE",
|
||||
If(self._start.r & self._start.re,
|
||||
NextState("START")
|
||||
)
|
||||
)
|
||||
fsm.act("START",
|
||||
self.sata_bist.start.eq(1),
|
||||
NextState("WAIT_DONE")
|
||||
)
|
||||
fsm.act("WAIT_DONE",
|
||||
If(self.sata_bist.done,
|
||||
NextState("CHECK_PREPARE")
|
||||
).Elif(self._stop.r & self._stop.re,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("CHECK_PREPARE",
|
||||
check_prepare.eq(1),
|
||||
NextState("START")
|
||||
)
|
||||
|
||||
self.sync += [
|
||||
If(check_prepare,
|
||||
ctrl_errors.eq(ctrl_errors + self.sata_bist.ctrl_errors),
|
||||
data_errors.eq(data_errors + self.sata_bist.data_errors),
|
||||
sector.eq(sector+4)
|
||||
)
|
||||
]
|
||||
|
||||
|
||||
class TestDesign(UART2WB, AutoCSR):
|
||||
default_platform = "kc705"
|
||||
csr_map = {
|
||||
|
|
@ -342,8 +169,7 @@ class TestDesign(UART2WB, AutoCSR):
|
|||
self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, host=True, speed="SATA2")
|
||||
self.sata_con = SATACON(self.sata_phy, sector_size=512, max_count=8)
|
||||
|
||||
#self.command_generator = CommandGenerator(self.sata_con, sector_size=512)
|
||||
self.bist = BIST(self.sata_con, sector_size=512)
|
||||
self.bist = SATABIST(self.sata_con)
|
||||
|
||||
self.clock_leds = ClockLeds(platform)
|
||||
|
||||
|
|
@ -380,7 +206,6 @@ class TestDesign(UART2WB, AutoCSR):
|
|||
self.sata_con.sink.ack,
|
||||
self.sata_con.sink.write,
|
||||
self.sata_con.sink.read,
|
||||
self.sata_con.sink.identify,
|
||||
|
||||
self.sata_con.source.stb,
|
||||
self.sata_con.source.sop,
|
||||
|
|
@ -388,7 +213,6 @@ class TestDesign(UART2WB, AutoCSR):
|
|||
self.sata_con.source.ack,
|
||||
self.sata_con.source.write,
|
||||
self.sata_con.source.read,
|
||||
self.sata_con.source.identify,
|
||||
self.sata_con.source.success,
|
||||
self.sata_con.source.failed,
|
||||
self.sata_con.source.data
|
||||
|
|
|
|||
|
|
@ -5,18 +5,44 @@ from tools import *
|
|||
sector_size = 512
|
||||
|
||||
wb.open()
|
||||
regs = wb.regs
|
||||
###
|
||||
regs.bist_start.write(1)
|
||||
last_sector = 0
|
||||
while True:
|
||||
class SATABISTDriver:
|
||||
def __init__(self, regs):
|
||||
self.regs = regs
|
||||
self.last_sector = 0
|
||||
self.last_time = time.time()
|
||||
self.last_errors = 0
|
||||
|
||||
def start_loopback(self, sector, count):
|
||||
self.regs.bist_start_sector.write(sector)
|
||||
self.regs.bist_count.write(count)
|
||||
self.regs.bist_stop.write(0)
|
||||
self.regs.bist_start.write(1)
|
||||
|
||||
def stop(self):
|
||||
self.regs.bist_stop.write(1)
|
||||
|
||||
def show_status(self):
|
||||
errors = self.regs.bist_errors.read() - self.last_errors
|
||||
self.last_errors += errors
|
||||
|
||||
sector = self.regs.bist_sector.read()
|
||||
n = sector - self.last_sector
|
||||
self.last_sector = sector
|
||||
|
||||
t = self.last_time - time.time()
|
||||
self.last_time = time.time()
|
||||
|
||||
print("%4.2f Mb/sec errors=%d sector=%d" %(n*512*8*2/(1024*1024), errors, sector))
|
||||
|
||||
bist = SATABISTDriver(wb.regs)
|
||||
try:
|
||||
bist.start_loopback(0, 4)
|
||||
while True:
|
||||
bist.show_status()
|
||||
time.sleep(1)
|
||||
sector = regs.bist_sector.read()
|
||||
n_sectors = sector - last_sector
|
||||
last_sector = sector
|
||||
n_bytes = n_sectors*sector_size*4*2
|
||||
ctrl_errors = regs.bist_ctrl_errors.read()
|
||||
data_errors = regs.bist_data_errors.read()
|
||||
print("%04d MB/s / data_errors %08d / ctrl_errors %08d " %(n_bytes/(1024*1024), data_errors, ctrl_errors))
|
||||
except KeyboardInterrupt:
|
||||
pass
|
||||
bist.stop()
|
||||
###
|
||||
wb.close()
|
||||
|
|
|
|||
|
|
@ -1,38 +0,0 @@
|
|||
import time
|
||||
from config import *
|
||||
from tools import *
|
||||
from miscope.host.drivers import MiLaDriver
|
||||
|
||||
mila = MiLaDriver(wb.regs, "mila")
|
||||
wb.open()
|
||||
regs = wb.regs
|
||||
###
|
||||
|
||||
cond = {
|
||||
#"sata_phy_source_source_payload_data" : primitives["R_RDY"],
|
||||
#"sata_phy_source_source_payload_data" : primitives["R_OK"],
|
||||
"sata_phy_source_source_payload_data" : primitives["X_RDY"],
|
||||
}
|
||||
|
||||
trigger = 0
|
||||
mask = 0
|
||||
for k, v in cond.items():
|
||||
trigger |= getattr(mila, k+"_o")*v
|
||||
mask |= getattr(mila, k+"_m")
|
||||
|
||||
mila.prog_term(port=0, trigger=trigger, mask=mask)
|
||||
mila.prog_sum("term")
|
||||
|
||||
# Trigger / wait / receive
|
||||
mila.trigger(offset=32, length=512)
|
||||
regs.command_generator_identify.write(1)
|
||||
mila.wait_done()
|
||||
mila.read()
|
||||
mila.export("dump.vcd")
|
||||
###
|
||||
wb.close()
|
||||
|
||||
print_link_trace(mila,
|
||||
tx_data_name="sata_phy_sink_sink_payload_data",
|
||||
rx_data_name="sata_phy_source_source_payload_data"
|
||||
)
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
from config import *
|
||||
from miscope.host.drivers import MiLaDriver
|
||||
|
||||
mila = MiLaDriver(wb.regs, "mila", use_rle=False)
|
||||
wb.open()
|
||||
###
|
||||
trigger0 = mila.cont_remover_source_stb_o*1
|
||||
mask0 = mila.cont_remover_source_stb_m
|
||||
|
||||
trigger0 = 0
|
||||
mask0 = 0
|
||||
|
||||
mila.prog_term(port=0, trigger=trigger0, mask=mask0)
|
||||
mila.prog_sum("term")
|
||||
|
||||
# Trigger / wait / receive
|
||||
mila.trigger(offset=32, length=1024)
|
||||
mila.wait_done()
|
||||
mila.read()
|
||||
mila.export("dump.vcd")
|
||||
mila.export("dump.csv")
|
||||
###
|
||||
wb.close()
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
import time
|
||||
from config import *
|
||||
from tools import *
|
||||
from miscope.host.drivers import MiLaDriver
|
||||
|
||||
mila = MiLaDriver(wb.regs, "mila")
|
||||
wb.open()
|
||||
regs = wb.regs
|
||||
###
|
||||
|
||||
cond = {
|
||||
#"sata_phy_source_source_payload_data" : primitives["R_RDY"],
|
||||
#"sata_phy_source_source_payload_data" : primitives["R_OK"],
|
||||
#"sata_phy_source_source_payload_data" : primitives["X_RDY"],
|
||||
"sata_con_source_source_stb" : 1,
|
||||
}
|
||||
|
||||
trigger = 0
|
||||
mask = 0
|
||||
for k, v in cond.items():
|
||||
trigger |= getattr(mila, k+"_o")*v
|
||||
mask |= getattr(mila, k+"_m")
|
||||
|
||||
mila.prog_term(port=0, trigger=trigger, mask=mask)
|
||||
mila.prog_sum("term")
|
||||
|
||||
# Trigger / wait / receive
|
||||
mila.trigger(offset=32, length=512)
|
||||
regs.command_generator_sector.write(0)
|
||||
regs.command_generator_count.write(1)
|
||||
regs.command_generator_read.write(1)
|
||||
mila.wait_done()
|
||||
mila.read()
|
||||
mila.export("dump.vcd")
|
||||
###
|
||||
wb.close()
|
||||
|
||||
print_link_trace(mila,
|
||||
tx_data_name="sata_phy_sink_sink_payload_data",
|
||||
rx_data_name="sata_phy_source_source_payload_data"
|
||||
)
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
import time
|
||||
from config import *
|
||||
from tools import *
|
||||
from miscope.host.drivers import MiLaDriver
|
||||
|
||||
mila = MiLaDriver(wb.regs, "mila")
|
||||
wb.open()
|
||||
regs = wb.regs
|
||||
###
|
||||
|
||||
cond = {
|
||||
#"sata_phy_source_source_payload_data" : primitives["R_RDY"],
|
||||
#"sata_phy_source_source_payload_data" : primitives["R_OK"],
|
||||
#"sata_phy_source_source_payload_data" : primitives["X_RDY"],
|
||||
"sata_con_source_source_stb" : 1,
|
||||
}
|
||||
|
||||
trigger = 0
|
||||
mask = 0
|
||||
for k, v in cond.items():
|
||||
trigger |= getattr(mila, k+"_o")*v
|
||||
mask |= getattr(mila, k+"_m")
|
||||
|
||||
mila.prog_term(port=0, trigger=trigger, mask=mask)
|
||||
mila.prog_sum("term")
|
||||
|
||||
# Trigger / wait / receive
|
||||
mila.trigger(offset=32, length=512)
|
||||
regs.command_generator_sector.write(0)
|
||||
regs.command_generator_count.write(1)
|
||||
regs.command_generator_data.write(0x12345678)
|
||||
regs.command_generator_write.write(1)
|
||||
mila.wait_done()
|
||||
mila.read()
|
||||
mila.export("dump.vcd")
|
||||
###
|
||||
wb.close()
|
||||
|
||||
print_link_trace(mila,
|
||||
tx_data_name="sata_phy_sink_sink_payload_data",
|
||||
rx_data_name="sata_phy_source_source_payload_data"
|
||||
)
|
||||
Loading…
Reference in a new issue