another attempt at fixing clock routing issues

build.py

@@ -18,8 +18,6 @@ TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
 """, clk50=platform.lookup_request("clk50"))
 
 	platform.add_platform_command("""
-INST "m1crg/pll" LOC="PLL_ADV_X0Y1";
-INST "m1crg/vga_clock_gen" LOC="DCM_X0Y6";
 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
 

verilog/m1crg/m1crg.v

@@ -209,6 +209,12 @@ BUFG bufg_x1(
 	.O(sys_clk)
 );
 
+wire clk50g;
+BUFG bufg_50(
+	.I(pllout4),
+	.O(clk50g)
+);
+
 wire clk2x_off;
 BUFG bufg_x2_offclk(
 	.I(pllout5),
@@ -253,7 +259,7 @@ ODDR2 #(
  * Ethernet PHY 
  */
 
-always @(posedge pllout4)
+always @(posedge clk50g)
 	eth_phy_clk_pad <= ~eth_phy_clk_pad;
 
 /* Let the synthesizer insert the appropriate buffers */
@@ -277,7 +283,7 @@ DCM_CLKGEN #(
 	.CLKFX180(),
 	.CLKFXDV(),
 	.STATUS(),
-	.CLKIN(pllout4),
+	.CLKIN(clk50g),
 	.FREEZEDCM(1'b0),
 	.PROGCLK(vga_progclk),
 	.PROGDATA(vga_progdata),