liteXXX cores: share same methodology for on-board tests

misoclib/com/liteeth/README

@@ -72,7 +72,7 @@ devel [AT] lists.m-labs.hk.
 5. Test design (only for KC705 for now):
   try to ping 192.168.1.40
   go to [..]/example_designs/test/
-  run ./make.py udp
+  run ./make.py test_udp
 
 6. Build and load Etherbone design (only for KC705 for now):
   python3 make.py -t etherbone all load-bitstream
@@ -80,7 +80,7 @@ devel [AT] lists.m-labs.hk.
 7. Test design (only for KC705 for now):
   try to ping 192.168.1.40
   go to [..]/example_designs/test/
-  run ./make.py etherbone
+  run ./make.py test_etherbone
 
 [> Simulations:
   Simulations are available in misoclib/com/liteeth/test/:

misoclib/com/liteeth/example_designs/test/make.py

@@ -29,5 +29,5 @@ if __name__ == "__main__":
 		return importlib.import_module(name)
 
 	for test in args.test:
-		t = _import("test_"+test)
+		t = _import(test)
 		t.main(wb)

misoclib/mem/litesata/README

@@ -100,7 +100,7 @@ devel [AT] lists.m-labs.hk.
 
 6. Test design (only for KC705 for now):
   go to [..]/example_designs/test/
-  run ./make.py --port your_serial_port bist
+  run ./bist.py --port your_serial_port
 
 7. If you only want to build the core and use it with your
    regular design flow:

misoclib/mem/litesata/example_designs/test/bist.py

@@ -2,7 +2,7 @@ import time
 import argparse
 import random as rand
 from collections import OrderedDict
-from config import *
+from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver
 
 KB = 1024
 MB = 1024*KB
@@ -128,6 +128,9 @@ def _get_args():
 		description="""\
 SATA BIST utility.
 """)
+	parser.add_argument("--port", default=2, help="UART port")
+	parser.add_argument("--baudrate", default=921600, help="UART baudrate")
+	parser.add_argument("--busword", default=32, help="CSR busword")
 	parser.add_argument("-s", "--transfer_size", default=1024, help="transfer sizes (in KB, up to 16MB)")
 	parser.add_argument("-l", "--total_length", default=256, help="total transfer length (in MB, up to HDD capacity)")
 	parser.add_argument("-n", "--loops", default=1, help="number of loop per transfer (allow more precision on speed calculation for small transfers)")
@@ -140,6 +143,7 @@ SATA BIST utility.
 
 if __name__ == "__main__":
 	args = _get_args()
+	wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
 	wb.open()
 	###
 	identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")

misoclib/mem/litesata/example_designs/test/config.py

@@ -1,9 +0,0 @@
-from litescope.host.driver.uart import LiteScopeUARTDriver
-
-csr_csv_file = "./csr.csv"
-busword = 32
-debug_wb = False
-
-com = 2
-baud = 921600
-wb = LiteScopeUARTDriver(com, baud, csr_csv_file, busword, debug_wb)

misoclib/mem/litesata/example_designs/test/make.py

@@ -0,0 +1,33 @@
+#!/usr/bin/env python3
+import argparse, importlib
+
+def _get_args():
+	parser = argparse.ArgumentParser()
+	parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
+	parser.add_argument("--port", default=2, help="UART port")
+	parser.add_argument("--baudrate", default=921600, help="UART baudrate")
+	parser.add_argument("--ip_address", default="192.168.1.40", help="Etherbone  IP address")
+	parser.add_argument("--udp_port", default=20000, help="Etherbone UDP port")
+	parser.add_argument("--busword", default=32, help="CSR busword")
+
+	parser.add_argument("test", nargs="+", help="specify a test")
+
+	return parser.parse_args()
+
+if __name__ == "__main__":
+	args = _get_args()
+	if args.bridge == "uart":
+		from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver
+		wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+	elif args.bridge == "etherbone":
+		from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver
+		wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
+	else:
+		ValueError("Invalid bridge {}".format(args.bridge))
+
+	def _import(name):
+		return importlib.import_module(name)
+
+	for test in args.test:
+		t = _import(test)
+		t.main(wb)

misoclib/mem/litesata/example_designs/test/test_la.py

@@ -1,71 +1,71 @@
 import sys
-from config import *
 from tools import *
-from bist import *
+from test_bist import *
 from litescope.host.driver.la import LiteScopeLADriver
 
-la = LiteScopeLADriver(wb.regs, "la")
+def main(wb):
-identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
+	la = LiteScopeLADriver(wb.regs, "la")
-generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist")
+	identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
-checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
+	generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist")
-wb.open()
+	checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
-regs = wb.regs
+	wb.open()
-###
+	regs = wb.regs
+	###
 
-trig = "now"
+	trig = "now"
-if len(sys.argv) < 2:
+	if len(sys.argv) < 2:
-	print("No trigger condition, triggering immediately!")
+		print("No trigger condition, triggering immediately!")
-else:
+	else:
-	trig = sys.argv[1]
+		trig = sys.argv[1]
 
-conditions = {}
+	conditions = {}
-conditions["now"] = {}
+	conditions["now"] = {}
-conditions["id_cmd"] = {
+	conditions["id_cmd"] = {
-	"sata_command_tx_sink_stb"				: 1,
+		"sata_command_tx_sink_stb"				: 1,
-	"sata_command_tx_sink_payload_identify"	: 1,
+		"sata_command_tx_sink_payload_identify"	: 1,
-}
+	}
-conditions["id_resp"] = {
+	conditions["id_resp"] = {
-	"source_source_payload_data" : primitives["X_RDY"],
+		"source_source_payload_data" : primitives["X_RDY"],
-}
+	}
-conditions["wr_cmd"] = {
+	conditions["wr_cmd"] = {
-	"sata_command_tx_sink_stb"			: 1,
+		"sata_command_tx_sink_stb"			: 1,
-	"sata_command_tx_sink_payload_write"	: 1,
+		"sata_command_tx_sink_payload_write"	: 1,
-}
+	}
-conditions["wr_resp"] = {
+	conditions["wr_resp"] = {
-	"sata_command_rx_source_stb"			: 1,
+		"sata_command_rx_source_stb"			: 1,
-	"sata_command_rx_source_payload_write"	: 1,
+		"sata_command_rx_source_payload_write"	: 1,
-}
+	}
-conditions["rd_cmd"] = {
+	conditions["rd_cmd"] = {
-	"sata_command_tx_sink_stb"			: 1,
+		"sata_command_tx_sink_stb"			: 1,
-	"sata_command_tx_sink_payload_read"	: 1,
+		"sata_command_tx_sink_payload_read"	: 1,
-}
+	}
-conditions["rd_resp"] = {
+	conditions["rd_resp"] = {
-	"sata_command_rx_source_stb"			: 1,
+		"sata_command_rx_source_stb"			: 1,
-	"sata_command_rx_source_payload_read"	: 1,
+		"sata_command_rx_source_payload_read"	: 1,
-}
+	}
 
-la.configure_term(port=0, cond=conditions[trig])
+	la.configure_term(port=0, cond=conditions[trig])
-la.configure_sum("term")
+	la.configure_sum("term")
 
-# Run Logic Analyzer
+	# Run Logic Analyzer
-la.run(offset=64, length=1024)
+	la.run(offset=64, length=1024)
 
-#identify.run(blocking=False)
+	#identify.run(blocking=False)
-generator.run(0, 2, 1, 0, blocking=False)
+	generator.run(0, 2, 1, 0, blocking=False)
-#checker.run(0, 2, 1, 0, blocking=False)
+	#checker.run(0, 2, 1, 0, blocking=False)
 
-while not la.done():
+	while not la.done():
-	pass
+		pass
 
-la.upload()
+	la.upload()
-la.save("dump.vcd")
+	la.save("dump.vcd")
-###
+	###
-wb.close()
+	wb.close()
 
-f = open("dump_link.txt", "w")
+	f = open("dump_link.txt", "w")
-data = link_trace(la,
+	data = link_trace(la,
-	tx_data_name="sink_sink_payload_data",
+		tx_data_name="sink_sink_payload_data",
-	rx_data_name="source_source_payload_data"
+		rx_data_name="source_source_payload_data"
-)
+	)
-f.write(data)
+	f.write(data)
-f.close()
+	f.close()

misoclib/mem/litesata/example_designs/test/test_regs.py

@@ -1,10 +1,9 @@
-from config import *
+def main(wb):
-
+	wb.open()
-wb.open()
+	regs = wb.regs
-regs = wb.regs
+	###
-###
+	print("sysid     : 0x%04x" %regs.identifier_sysid.read())
-print("sysid     : 0x%04x" %regs.identifier_sysid.read())
+	print("revision  : 0x%04x" %regs.identifier_revision.read())
-print("revision  : 0x%04x" %regs.identifier_revision.read())
+	print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
-print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
+	###
-###
+	wb.close()
-wb.close()

misoclib/tools/litescope/README

@@ -91,12 +91,12 @@ devel [AT] lists.m-labs.hk.
 
 5. Test design:
   go to [..]/example_designs/test/ and run:
-  ./make.py --port your_serial_port io (will blink leds)
+  ./make.py --port your_serial_port test_io (will blink leds)
-  ./make.py --port your_serial_port la (will capture counter)
+  ./make.py --port your_serial_port test_la (will capture counter)
 
   tests can also be executed over Etherbone (provided with LiteEth):
-  ./make.py --ip_address fpga_ip_address io
+  ./make.py --ip_address fpga_ip_address test_io
-  ./make.py --ip_address fpga_ip_address la
+  ./make.py --ip_address fpga_ip_address test_la
 
 [> Simulations:
   XXX convert simulations

misoclib/tools/litescope/example_designs/test/make.py

@@ -29,5 +29,5 @@ if __name__ == "__main__":
 		return importlib.import_module(name)
 
 	for test in args.test:
-		t = _import("test_"+test)
+		t = _import(test)
 		t.main(wb)