Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

tools/litex_json2dts_linux: added isa-base,isa-extensions required by kernel > 6.6.0 in replacement to isa

This commit is contained in:
Gwenhael Goavec-Merou 2024-03-21 20:53:19 +01:00
parent 29aa8f0771
commit 68108e396d
1 changed files with 13 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
litex/tools/litex_json2dts_linux.py
View File

@ -32,7 +32,9 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
ncpus = int(d["constants"].get("config_cpu_count", 1)) ncpus = int(d["constants"].get("config_cpu_count", 1))
cpu_name = d["constants"].get("config_cpu_name") cpu_name = d["constants"].get("config_cpu_name")
cpu_arch = cpu_architectures[cpu_name] cpu_arch = cpu_architectures[cpu_name]
cpu_isa = d["constants"].get("config_cpu_isa", None) cpu_isa = d["constants"].get("config_cpu_isa", None) # kernel < 6.6.0
cpu_isa_base = cpu_isa[:5] # kernel >= 6.6.0
cpu_isa_extensions = "\"i\", \"m\", \"a\"" # kernel >= 6.6.0
cpu_mmu = d["constants"].get("config_cpu_mmu", None) cpu_mmu = d["constants"].get("config_cpu_mmu", None)
# Header --------------------------------------------------------------------------------------- # Header ---------------------------------------------------------------------------------------
@ -152,7 +154,6 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
# Rocket specific attributes # Rocket specific attributes
if ("rocket" in cpu_name): if ("rocket" in cpu_name):
cpu_isa = cpu_isa.replace("2p0_", "")
extra_attr = """ extra_attr = """
hardware-exec-breakpoint-count = <1>; hardware-exec-breakpoint-count = <1>;
next-level-cache = <&memory>; next-level-cache = <&memory>;
@ -190,6 +191,8 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
device_type = "cpu"; device_type = "cpu";
compatible = "riscv"; compatible = "riscv";
riscv,isa = "{cpu_isa}"; riscv,isa = "{cpu_isa}";
riscv,isa-base = "{cpu_isa_base}";
riscv,isa-extensions = {cpu_isa_extensions};
mmu-type = "riscv,{cpu_mmu}"; mmu-type = "riscv,{cpu_mmu}";
reg = <{cpu}>; reg = <{cpu}>;
clock-frequency = <{sys_clk_freq}>; clock-frequency = <{sys_clk_freq}>;
@ -206,7 +209,9 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
}}; }};
""".format(cpu=cpu, irq=cpu, """.format(cpu=cpu, irq=cpu,
sys_clk_freq = d["constants"]["config_clock_frequency"], sys_clk_freq = d["constants"]["config_clock_frequency"],
cpu_isa = cpu_isa, cpu_isa = cpu_isa, # for kernel < 6.6.0
cpu_isa_base = cpu_isa_base, # for kernel >= 6.6.0
cpu_isa_extensions = cpu_isa_extensions, # for kernel >= 6.6.0
cpu_mmu = cpu_mmu, cpu_mmu = cpu_mmu,
cache_desc = cache_desc, cache_desc = cache_desc,
tlb_desc = tlb_desc, tlb_desc = tlb_desc,