Change AXI interface and tidy code
Inspired by parts of https://github.com/peteut/migen-misc/
This commit is contained in:
Sergiusz Bazanski
parent
512ed2b3d6
commit
688f26cc32
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@ -13,33 +13,43 @@ from litex.soc.interconnect import csr_bus
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# Layout of AXI4 Lite Bus
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_layout = [
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# Write Address
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("awaddr", "address_width", DIR_M_TO_S),
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("awprot", 3, DIR_M_TO_S),
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("awvalid", 1, DIR_M_TO_S),
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("awready", 1, DIR_S_TO_M),
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("aw", [
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("addr", "address_width", DIR_M_TO_S),
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("prot", 3, DIR_M_TO_S),
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("valid", 1, DIR_M_TO_S),
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("ready", 1, DIR_S_TO_M),
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]),
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# Write Data
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("wdata", "data_width", DIR_M_TO_S),
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("wstrb", "strb_width", DIR_M_TO_S),
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("wvalid", 1, DIR_M_TO_S),
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("wready", 1, DIR_S_TO_M),
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("w", [
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("data", "data_width", DIR_M_TO_S),
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("strb", "strb_width", DIR_M_TO_S),
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("valid", 1, DIR_M_TO_S),
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("ready", 1, DIR_S_TO_M),
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]),
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# Write Response
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("bresp", 2, DIR_S_TO_M),
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("bvalid", 1, DIR_S_TO_M),
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("bready", 1, DIR_M_TO_S),
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("b", [
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("resp", 2, DIR_S_TO_M),
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("valid", 1, DIR_S_TO_M),
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("ready", 1, DIR_M_TO_S),
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]),
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# Read Address
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("araddr", "address_width", DIR_M_TO_S),
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("arprot", 3, DIR_M_TO_S),
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("arvalid", 1, DIR_M_TO_S),
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("arready", 1, DIR_S_TO_M),
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("ar", [
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("addr", "address_width", DIR_M_TO_S),
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("prot", 3, DIR_M_TO_S),
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("valid", 1, DIR_M_TO_S),
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("ready", 1, DIR_S_TO_M),
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]),
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# Read Data
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("rdata", "data_width", DIR_S_TO_M),
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("rresp", 2, DIR_S_TO_M),
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("rvalid", 1, DIR_S_TO_M),
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("rready", 1, DIR_M_TO_S),
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("r", [
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("data", "data_width", DIR_S_TO_M),
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("resp", 2, DIR_S_TO_M),
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("valid", 1, DIR_S_TO_M),
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("ready", 1, DIR_M_TO_S),
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]),
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]
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class Interface(Record):
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@ -66,12 +76,14 @@ class AXILite2CSR(Module):
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including writes.
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"""
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def __init__(self, bus_interface_axi, bus_interface_csr):
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self.axi = bus_interface_axi
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self.csr = bus_interface_csr
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def __init__(self, bus_axi, bus_csr):
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self.axi = axi = bus_axi
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self.csr = csr = bus_csr
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###
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ar, r, aw, w, b = axi.ar, axi.r, axi.aw, axi.w, axi.b
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# Machine is currently busy talking to CSR, hold your horses.
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busy = Signal()
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@ -80,89 +92,88 @@ class AXILite2CSR(Module):
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# A read transaction is happening on the bus.
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read_transaction = Signal()
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self.comb += [
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write_transaction.eq(self.axi.awvalid & self.axi.awready & self.axi.wvalid & self.axi.wready),
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read_transaction.eq(self.axi.arvalid & self.axi.arready),
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write_transaction.eq(aw.valid & aw.ready & w.valid & w.ready),
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read_transaction.eq(ar.valid & ar.ready),
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]
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# Write transaction generation.
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self.sync += [
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self.axi.awready.eq(0),
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self.axi.wready.eq(0),
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If(self.axi.awvalid & self.axi.wvalid,
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If(~self.axi.awready & ~busy & ~self.axi.arvalid,
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self.axi.awready.eq(1),
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self.axi.wready.eq(1)
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aw.ready.eq(0),
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w.ready.eq(0),
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If(aw.valid & w.valid,
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If(~aw.ready & ~busy & ~ar.valid,
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aw.ready.eq(1),
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w.ready.eq(1)
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)
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)
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]
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# Write response generation.
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self.sync += [
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self.axi.bvalid.eq(0),
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b.valid.eq(0),
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If(write_transaction,
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If(self.axi.bready & ~self.axi.bvalid,
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self.axi.bvalid.eq(1),
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If(b.ready & ~b.valid,
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b.valid.eq(1),
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# Response 0 -> OKAY
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self.axi.bresp.eq(0),
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b.resp.eq(0),
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)
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)
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]
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# Read transaction generation.
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self.sync += [
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self.axi.arready.eq(0),
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If(self.axi.arvalid & ~self.axi.arready & ~busy,
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self.axi.arready.eq(1),
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ar.ready.eq(0),
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If(ar.valid & ~ar.ready & ~busy,
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ar.ready.eq(1),
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)
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]
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# Registered data to be written to CSR, set by FSM.
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wdata = Signal(self.csr.dat_w.nbits)
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wdata = Signal(csr.dat_w.nbits)
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# Combinatorial byte address to assert on CSR bus, driven by FSM.
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addr = Signal(self.axi.araddr.nbits)
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addr = Signal(ar.addr.nbits)
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# Drive AXI & CSR combinatorial signals.
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self.comb += [
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self.csr.adr.eq(addr >>
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int(math.log(self.axi.rdata.nbits//8, 2.0))),
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self.csr.dat_w.eq(wdata),
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csr.adr.eq(addr >> int(math.log(r.data.nbits//8, 2.0))),
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csr.dat_w.eq(wdata),
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self.axi.rdata.eq(self.csr.dat_r),
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self.axi.rresp.eq(0),
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r.data.eq(csr.dat_r),
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r.resp.eq(0),
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]
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# CSR interaction FSM.
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self.submodules.fsm = FSM(reset_state='IDLE')
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self.submodules.fsm = fsm = FSM(reset_state='IDLE')
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self.comb += [
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busy.eq(~self.fsm.ongoing('IDLE')),
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self.axi.rvalid.eq(self.fsm.ongoing('READING')),
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self.csr.we.eq(self.fsm.ongoing('WRITING')),
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busy.eq(~fsm.ongoing('IDLE')),
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r.valid.eq(fsm.ongoing('READING')),
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csr.we.eq(fsm.ongoing('WRITING')),
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]
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# Idle state - wait for a transaction to happen on AXI. Immediately
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# assert read/write address on CSR if such an transaction is occuring.
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self.fsm.act('IDLE',
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fsm.act('IDLE',
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If(read_transaction,
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addr.eq(self.axi.araddr),
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addr.eq(ar.addr),
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NextState('READING'),
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).Elif(write_transaction,
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addr.eq(self.axi.awaddr),
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addr.eq(aw.addr),
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# Register data from AXI.
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NextValue(wdata, self.axi.wdata),
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NextValue(wdata, w.data),
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NextState('WRITING'),
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)
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)
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# Perform write to CSR.
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self.fsm.act('WRITING',
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addr.eq(self.axi.awaddr),
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fsm.act('WRITING',
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addr.eq(aw.addr),
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# CSR writes are single cycle, go back to IDLE.
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NextState('IDLE'),
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)
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# Respond to read to AXI.
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self.fsm.act('READING',
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addr.eq(self.axi.araddr),
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fsm.act('READING',
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addr.eq(ar.addr),
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# If AXI master is ready to receive data, go back to IDLE.
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If(self.axi.rready,
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If(r.ready,
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NextState('IDLE'),
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)
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)
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@ -183,8 +194,10 @@ def test_axilite2csr():
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self.axi = Interface(data_width=32, address_width=14)
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self.submodules.holder = CSRHolder()
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self.submodules.dut = AXILite2CSR(self.axi, self.csr)
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self.submodules.csrbankarray = csr_bus.CSRBankArray(self, self.map_csr, data_width=32, address_width=12)
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self.submodules.csrcon = csr_bus.Interconnect(self.csr, self.csrbankarray.get_buses())
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self.submodules.csrbankarray = csr_bus.CSRBankArray(
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self, self.map_csr, data_width=32, address_width=12)
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self.submodules.csrcon = csr_bus.Interconnect(
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self.csr, self.csrbankarray.get_buses())
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def map_csr(self, name, memory):
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return {
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@ -192,64 +205,68 @@ def test_axilite2csr():
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}[name]
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def testbench_write_read(dut):
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axi = dut.axi
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for _ in range(8):
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yield
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# Write test
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yield dut.axi.awvalid.eq(1)
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yield dut.axi.awaddr.eq(4)
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yield dut.axi.wvalid.eq(1)
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yield dut.axi.bready.eq(1)
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yield dut.axi.wdata.eq(0x2137)
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yield axi.aw.valid.eq(1)
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yield axi.aw.addr.eq(4)
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yield axi.w.valid.eq(1)
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yield axi.b.ready.eq(1)
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yield axi.w.data.eq(0x2137)
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while (yield dut.axi.awready) != 1:
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while (yield axi.aw.ready) != 1:
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yield
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while (yield dut.axi.wready) != 1:
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while (yield axi.w.ready) != 1:
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yield
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yield dut.axi.awvalid.eq(0)
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yield dut.axi.wvalid.eq(0)
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yield axi.aw.valid.eq(0)
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yield axi.w.valid.eq(0)
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for _ in range(8):
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yield
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# Read test
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yield dut.axi.arvalid.eq(1)
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yield dut.axi.rready.eq(1)
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yield dut.axi.araddr.eq(4)
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yield axi.ar.valid.eq(1)
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yield axi.r.ready.eq(1)
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yield axi.ar.addr.eq(4)
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while (yield dut.axi.arready != 1):
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while (yield axi.ar.ready != 1):
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yield
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yield dut.axi.arvalid.eq(0)
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while (yield dut.axi.rvalid != 1):
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yield axi.ar.valid.eq(0)
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while (yield axi.r.valid != 1):
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yield
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yield dut.axi.rready.eq(0)
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yield axi.r.ready.eq(0)
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read = yield dut.axi.rdata
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read = yield axi.r.data
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assert read == 0x2137
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for _ in range(8):
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yield
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def testbench_simultaneous(dut):
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axi = dut.axi
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for _ in range(8):
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yield
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# Write
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yield dut.axi.awvalid.eq(1)
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yield dut.axi.awaddr.eq(2)
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yield dut.axi.wvalid.eq(1)
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yield dut.axi.bready.eq(1)
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yield dut.axi.wdata.eq(0x2137)
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yield axi.aw.valid.eq(1)
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yield axi.aw.addr.eq(2)
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yield axi.w.valid.eq(1)
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yield axi.b.ready.eq(1)
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yield axi.w.data.eq(0x2137)
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# Read
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yield dut.axi.arvalid.eq(1)
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yield dut.axi.rready.eq(1)
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yield dut.axi.araddr.eq(2)
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yield axi.ar.valid.eq(1)
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yield axi.r.ready.eq(1)
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yield axi.ar.addr.eq(2)
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yield
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yield
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is_reading = yield dut.axi.arready
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is_writing = yield dut.axi.awready
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is_reading = yield axi.ar.ready
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is_writing = yield axi.aw.ready
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assert is_reading
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assert not is_writing
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