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soc_sdram: limit main_ram to 512MB for now

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Otherwise breaks linux-on-litex-vexriscv for targets with 1GB of ram, could
be removed when mem_map will be reworked on linux-on-litex-vexriscv.
This commit is contained in:
Florent Kermarrec 2019-07-09 12:14:50 +02:00
parent ccbf141850
commit 68a503174c
1 changed files with 1 additions and 0 deletions
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litex/soc/integration/soc_sdram.py
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@ -69,6 +69,7 @@ class SoCSDRAM(SoCCore):
main_ram_size = 2**(geom_settings.bankbits +
geom_settings.rowbits +
geom_settings.colbits)*phy.settings.databits//8
main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
self.config["L2_SIZE"] = self.l2_size
# add a Wishbone interface to the DRAM