add Trigger
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@ -145,10 +145,9 @@ class Sum:
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self.pipe = pipe
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self.pipe = pipe
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self.prog_mode = prog_mode
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self.prog_mode = prog_mode
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assert (size <= 4), "size > 4 (This version support only non cascadable SRL16)"
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assert (size <= 4), "size > 4 (This version support only non cascadable SRL16)"
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self.i0 = Signal()
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self.i = Array(Signal() for j in range(4))
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self.i1 = Signal()
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for j in range(4):
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self.i2 = Signal()
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self.i[j].name_override = "i%d"%j
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self.i3 = Signal()
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self._ce = Signal()
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self._ce = Signal()
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self._shift_in = Signal()
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self._shift_in = Signal()
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@ -197,10 +196,10 @@ class Sum:
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inst = [
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inst = [
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Instance("SRLC16E",
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Instance("SRLC16E",
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[
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[
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("a0", self.i0),
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("a0", self.i[0]),
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("a1", self.i1),
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("a1", self.i[1]),
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("a2", self.i2),
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("a2", self.i[2]),
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("a3", self.i3),
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("a3", self.i[3]),
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("ce", self._ce),
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("ce", self._ce),
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("d", self._shift_in)
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("d", self._shift_in)
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] , [
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] , [
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@ -221,6 +220,45 @@ class Sum:
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return Fragment(comb=comb,sync=sync,instances=inst)
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return Fragment(comb=comb,sync=sync,instances=inst)
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class Trigger:
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def __init__(self,address, trig_width, dat_width, ports):
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self.trig_width = trig_width
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self.dat_width = dat_width
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self.ports = ports
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assert (len(self.ports) <= 4), "Nb Ports > 4 (This version support 4 ports Max)"
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self.in_trig = Signal(BV(self.trig_width))
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self.in_dat = Signal(BV(self.dat_width))
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self.hit = Signal()
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self.dat = Signal(BV(self.dat_width))
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def get_fragment(self):
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comb = []
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sync = []
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# Connect in_trig to input of trig elements
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comb+= [port.i.eq(self.in_trig) for port in self.ports]
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# Connect output of trig elements to sum
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# Todo : Add sum tree to have more that 4 inputs
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_sum = Sum(len(self.ports))
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comb+= [_sum.i[j].eq(self.ports[j].o) for j in range(len(self.ports))]
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# Connect sum ouput to hit
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comb+= [self.hit.eq(_sum.o)]
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# Add ports & sum to frag
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frag = _sum.get_fragment()
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for port in self.ports:
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frag += port.get_fragment()
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comb+= [self.dat.eq(self.in_dat)]
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return frag + _sum.get_fragment() + Fragment(comb=comb, sync=sync)
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class Storage:
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class Storage:
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def __init__(self, width, depth):
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def __init__(self, width, depth):
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self.width = width
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self.width = width
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@ -389,6 +427,9 @@ class Recorder:
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self.storage.get_fragment()+self.sequencer.get_fragment()+\
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self.storage.get_fragment()+self.sequencer.get_fragment()+\
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Fragment(comb=comb, sync=sync)
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Fragment(comb=comb, sync=sync)
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class MigCon:
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class MigCon:
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pass
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pass
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14
top.py
14
top.py
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@ -66,6 +66,16 @@ import migScope
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#
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#
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#Test Recorder
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#Test Recorder
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#
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#
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recorder = migScope.Recorder(0,32,1024)
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#recorder = migScope.Recorder(0,32,1024)
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v = verilog.convert(recorder.get_fragment())
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#v = verilog.convert(recorder.get_fragment())
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#print(v)
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term0 = migScope.Term(32)
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term1 = migScope.Term(32)
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term2 = migScope.Term(32)
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term3 = migScope.Term(32)
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trigger0 = migScope.Trigger(0,32,64,[term0, term1, term2, term3])
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v = verilog.convert(trigger0.get_fragment())
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print(v)
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print(v)
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