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bus/wishbone2asmi: fix cache tag size

This commit is contained in:
Sebastien Bourdeauducq 2012-05-15 15:18:03 +02:00
parent 0bea1e2589
commit 68cd445662
1 changed files with 2 additions and 2 deletions
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4
migen/bus/wishbone2asmi.py
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@ -29,7 +29,7 @@ class WB2ASMI:
offsetbits = log2_int(adw//32) offsetbits = log2_int(adw//32)
addressbits = aaw + offsetbits addressbits = aaw + offsetbits
linebits = log2_int(self.cachesize) - offsetbits linebits = log2_int(self.cachesize) - offsetbits
tagbits = aaw - linebits tagbits = addressbits - linebits
adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits) adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
# Data memory # Data memory
@ -63,7 +63,7 @@ class WB2ASMI:
] ]
# Tag memory # Tag memory
tag_layout = [("tag", BV(linebits)), ("dirty", BV(1))] tag_layout = [("tag", BV(tagbits)), ("dirty", BV(1))]
tag_do = Record(tag_layout) tag_do = Record(tag_layout)
tag_do_raw = tag_do.to_signal(comb, False) tag_do_raw = tag_do.to_signal(comb, False)
tag_di = Record(tag_layout) tag_di = Record(tag_layout)