boards: avoid duplicating platforms that can be found in migen/litex-buildenv
The platforms that are kept are the ones used for litex development.
This commit is contained in:
Florent Kermarrec
parent
041bf41226
commit
68e1dfca28
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@ -1,125 +0,0 @@
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# This file is Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
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_io = [
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("user_led", 0, Pins("E18"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("F13"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("E13"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("H15"), IOStandard("LVCMOS33")),
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("rgb_led", 0,
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Subsignal("r", Pins("J15")),
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Subsignal("g", Pins("G17")),
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Subsignal("b", Pins("F15")),
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IOStandard("LVCMOS33")
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),
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("rgb_led", 1,
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Subsignal("r", Pins("E15")),
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Subsignal("g", Pins("F18")),
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Subsignal("b", Pins("E14")),
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IOStandard("LVCMOS33")
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),
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("user_sw", 0, Pins("H14"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("H18"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("G18"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("M5"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("G15"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("K16"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("J16"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("H13"), IOStandard("LVCMOS33")),
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("clk100", 0, Pins("R2"), IOStandard("SSTL135")),
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("cpu_reset", 0, Pins("C18"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("R12")),
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Subsignal("rx", Pins("V12")),
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IOStandard("LVCMOS33")),
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("spi", 0,
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Subsignal("clk", Pins("G16")),
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Subsignal("cs_n", Pins("H16")),
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Subsignal("mosi", Pins("H17")),
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Subsignal("miso", Pins("K14")),
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IOStandard("LVCMOS33")
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),
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("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("M13")),
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Subsignal("dq", Pins("K17", "K18", "L14", "M15")),
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IOStandard("LVCMOS33")
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),
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("spiflash", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("M13")),
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Subsignal("mosi", Pins("K17")),
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Subsignal("miso", Pins("K18")),
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Subsignal("wp", Pins("L14")),
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Subsignal("hold", Pins("M15")),
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IOStandard("LVCMOS33")
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"U2 R4 V2 V4 T3 R7 V6 T6",
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"U7 V7 P6 T5 R6 U6"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("V5 T1 U3"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("U1"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("V3"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("P7"), IOStandard("SSTL135")),
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Subsignal("cs_n", Pins("R3"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("K4 M3"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"K2 K3 L4 M6 K6 M4 L5 L6",
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"N4 R1 N1 N5 M2 P1 M1 P2"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("K1 N3"), IOStandard("DIFF_SSTL135")),
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Subsignal("dqs_n", Pins("L1 N2"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_p", Pins("R5"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("T4"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("T2"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("P5"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("J6"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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]
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_connectors = [
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("pmoda", "L17 L18 M14 N14 M16 M17 M18 N18"),
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("pmodb", "P17 P18 R18 T18 P14 P15 N15 P16"),
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("pmodc", "U15 V16 U17 U18 U16 P13 R13 V14"),
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("pmodd", "V15 U12 V13 T12 T13 R11 T11 U11")
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]
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 10.0
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def __init__(self, toolchain="vivado", programmer="vivado"):
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XilinxPlatform.__init__(self, "xc7s50csga324-1", _io, _connectors,
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toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.programmer = programmer
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
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def create_programmer(self):
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if self.programmer == "xc3sprog":
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return XC3SProg("nexys4")
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elif self.programmer == "vivado":
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return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
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else:
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raise ValueError("{} programmer is not supported"
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.format(self.programmer))
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@ -1,47 +0,0 @@
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import IceStormProgrammer
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_io = [
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("user_led", 0, Pins("B5"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("B4"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("A2"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("A1"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("C5"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("C4"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("B3"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("C3"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("rx", Pins("B10")),
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Subsignal("tx", Pins("B12"), Misc("PULLUP")),
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Subsignal("rts", Pins("B13"), Misc("PULLUP")),
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Subsignal("cts", Pins("A15"), Misc("PULLUP")),
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Subsignal("dtr", Pins("A16"), Misc("PULLUP")),
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Subsignal("dsr", Pins("B14"), Misc("PULLUP")),
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Subsignal("dcd", Pins("B15"), Misc("PULLUP")),
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IOStandard("LVCMOS33"),
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("R12"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("R11"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("P12"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("P11"), IOStandard("LVCMOS33")),
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),
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("clk12", 0, Pins("J3"), IOStandard("LVCMOS33"))
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]
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class Platform(LatticePlatform):
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default_clk_name = "clk12"
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default_clk_period = 83.333
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def __init__(self):
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LatticePlatform.__init__(self, "ice40-hx8k-ct256", _io,
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toolchain="icestorm")
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def create_programmer(self):
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return IceStormProgrammer()
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@ -1,57 +0,0 @@
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import IceStormProgrammer
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_io = [
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("user_led", 0, Pins("99"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("98"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("97"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("96"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("95"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("rx", Pins("9")),
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Subsignal("tx", Pins("8"), Misc("PULLUP")),
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Subsignal("rts", Pins("7"), Misc("PULLUP")),
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Subsignal("cts", Pins("4"), Misc("PULLUP")),
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Subsignal("dtr", Pins("3"), Misc("PULLUP")),
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Subsignal("dsr", Pins("2"), Misc("PULLUP")),
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Subsignal("dcd", Pins("1"), Misc("PULLUP")),
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IOStandard("LVTTL"),
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),
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("irda", 0,
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Subsignal("rx", Pins("106")),
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Subsignal("tx", Pins("105")),
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Subsignal("sd", Pins("107")),
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IOStandard("LVCMOS33")
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("71"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("70"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("67"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("68"), IOStandard("LVCMOS33"))
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),
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("clk12", 0, Pins("21"), IOStandard("LVCMOS33"))
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]
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_connectors = [
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("GPIO0", "44 45 47 48 56 60 61 62"),
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("GPIO1", "119 118 117 116 115 114 113 112"),
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("PMOD", "78 79 80 81 87 88 90 91")
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]
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class Platform(LatticePlatform):
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default_clk_name = "clk12"
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default_clk_period = 83.333
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def __init__(self):
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LatticePlatform.__init__(self, "ice40-hx1k-tq144", _io, _connectors,
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toolchain="icestorm")
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def create_programmer(self):
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return IceStormProgrammer()
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@ -1,207 +0,0 @@
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# This file is Copyright (c) 2015, 2017 William D. Jones <thor0505@comcast.net>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.xilinx.programmer import XC3SProg
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_io = [
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("clk50", 0, Pins("P43"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("P41"), IOStandard("LVTTL")),
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# The serial interface and flash memory have a shared SPI bus.
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# FPGA is secondary
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("spiserial", 0,
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Subsignal("cs_n", Pins("P39"), IOStandard("LVTTL")),
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Subsignal("clk", Pins("P53"), IOStandard("LVTTL")),
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Subsignal("mosi", Pins("P46"), IOStandard("LVTTL")),
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Subsignal("miso", Pins("P51"), IOStandard("LVTTL"))
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),
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# FPGA is primary
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("spiflash", 0,
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Subsignal("cs_n", Pins("P27"), IOStandard("LVTTL")),
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Subsignal("clk", Pins("P53"), IOStandard("LVTTL")),
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Subsignal("mosi", Pins("P46"), IOStandard("LVTTL")),
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Subsignal("miso", Pins("P51"), IOStandard("LVTTL"))
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),
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("spiflash2x", 0,
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Subsignal("cs_n", Pins("P27")),
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Subsignal("clk", Pins("P53")),
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Subsignal("dq", Pins("P46", "P51")),
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IOStandard("LVTTL"), Misc("SLEW=FAST")
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),
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# ADC over SPI- FPGA is primary
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("adc", 0,
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Subsignal("cs_n", Pins("P12"), IOStandard("LVTTL")),
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Subsignal("clk", Pins("P9"), IOStandard("LVTTL")),
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Subsignal("mosi", Pins("P10"), IOStandard("LVTTL")),
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Subsignal("miso", Pins("P21"), IOStandard("LVTTL"))
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),
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# GPIO control- SRAM and connectors are shared: these pins control how
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# to access each. Recommended to combine with gpio_sram_bus extension,
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# since these pins are related but not exposed on connectors.
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("gpio_ctl", 0,
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Subsignal("ce_n", Pins("P3")), # Memory chip-enable. Called MEM_CEN
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# in schematic.
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Subsignal("bussw_oe_n", Pins("P30")), # 5V tolerant GPIO is shared
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# w/ memory using this pin.
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IOStandard("LVTTL"), Misc("SLEW=FAST")
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)
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]
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# Perhaps define some connectors as having a specific purpose- i.e. a 5V GPIO
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# bus with data, peripheral-select, and control signals?
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_connectors = [
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("GPIO", """P59 P60 P61 P62 P64 P57
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P56 P52 P50 P49 P85 P84
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P83 P78 P77 P65 P70 P71
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P72 P73 P5 P4 P6 P98
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P94 P93 P90 P89 P88 P86"""), # 5V I/O- LVTTL
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("DIO", "P20 P32 P33 P34 P35 P36 P37"), # Fast 3.3V IO (Directly attached
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# to FPGA)- LVCMOS33
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("CLKIO", "P40 P44"), # Clock IO (Can be used as GPIO)- LVCMOS33
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("INPUT", "P68 P97 P7 P82"), # Input-only pins- LVCMOS33
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("LED", "P13 P15 P16 P19"), # LEDs can be used as pins as well- LVTTL.
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("PMOD", "P5 P4 P6 P98 P94 P93 P90 P89") # Baseboard PMOD.
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# Overlaps w/ GPIO bus.
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]
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# Some default useful extensions- use platform.add_extension() to use, e.g.
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# from migen.build.platforms import mercury
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# plat = mercury.Platform()
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# plat.add_extension(mercury.gpio_sram)
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# SRAM and 5V-tolerant I/O share a parallel bus on 200k gate version. The SRAM
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# controller needs to take care of switching the bus between the two. Meant to
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# be Cat() into one GPIO bus, and combined with gpio_ctl.
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gpio_sram = [
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("gpio_sram_bus", 0,
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Subsignal("a", Pins("""GPIO:0 GPIO:1 GPIO:2 GPIO:3
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GPIO:4 GPIO:5 GPIO:6 GPIO:7
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GPIO:8 GPIO:9 GPIO:10 GPIO:11
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GPIO:12 GPIO:13 GPIO:14 GPIO:15
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GPIO:16 GPIO:17 GPIO:18 GPIO:19""")),
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# A19 is actually unused- free for GPIO
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# 8-bit data bus
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Subsignal("d", Pins("""GPIO:20 GPIO:21 GPIO:22 GPIO:23
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GPIO:24 GPIO:25 GPIO:26 GPIO:27""")),
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Subsignal("we_n", Pins("GPIO:28")),
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Subsignal("unused", Pins("GPIO:29")), # Only used by GPIO.
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# Subsignal("oe_n", Pins()), # If OE wasn't tied to ground on Mercury,
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# this pin would be here.
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IOStandard("LVTTL"), Misc("SLEW=FAST")
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)
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]
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# The "serial port" is in fact over SPI. The creators of the board provide a
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# VHDL file for talking over this interface. In light of space constraints and
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# the fact that both the FT245RL and FPGA can BOTH be SPI primaries, however,
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# it may be necessary to sacrifice two "high-speed" (DIO, INPUT) pins instead.
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serial = [
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("serial", 0,
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Subsignal("tx", Pins("DIO:0"), IOStandard("LVCMOS33")), # FTDI D1
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Subsignal("rx", Pins("INPUT:0"), IOStandard("LVCMOS33")) # FTDI D0
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)
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]
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leds = [
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("user_led", 0, Pins("LED:0"), IOStandard("LVTTL")),
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("user_led", 1, Pins("LED:1"), IOStandard("LVTTL")),
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("user_led", 2, Pins("LED:2"), IOStandard("LVTTL")),
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("user_led", 3, Pins("LED:3"), IOStandard("LVTTL"))
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]
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# The remaining peripherals only make sense w/ the Baseboard installed.
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# See: http://www.micro-nova.com/mercury-baseboard/
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sw = [
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("sw", 0, Pins("GPIO:0"), IOStandard("LVTTL")),
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("sw", 1, Pins("GPIO:1"), IOStandard("LVTTL")),
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("sw", 2, Pins("GPIO:2"), IOStandard("LVTTL")),
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("sw", 3, Pins("GPIO:3"), IOStandard("LVTTL")),
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("sw", 4, Pins("GPIO:4"), IOStandard("LVTTL")),
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("sw", 5, Pins("GPIO:5"), IOStandard("LVTTL")),
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("sw", 6, Pins("GPIO:6"), IOStandard("LVTTL")),
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("sw", 7, Pins("GPIO:7"), IOStandard("LVTTL"))
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]
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user_btn = [
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("user_btn", 1, Pins("INPUT:0"), IOStandard("LVTTL")),
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("user_btn", 2, Pins("INPUT:1"), IOStandard("LVTTL")),
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("user_btn", 3, Pins("INPUT:2"), IOStandard("LVTTL")),
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("user_btn", 4, Pins("INPUT:3"), IOStandard("LVTTL"))
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]
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vga = [
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("vga_out", 0,
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Subsignal("hsync_n", Pins("LED:2"), IOStandard("LVCMOS33"),
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Misc("SLEW=FAST")),
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Subsignal("vsync_n", Pins("LED:3"), IOStandard("LVCMOS33"),
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Misc("SLEW=FAST")),
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Subsignal("r", Pins("DIO:0 DIO:1 DIO:2"), IOStandard("LVCMOS33"),
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Misc("SLEW=FAST")),
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Subsignal("g", Pins("DIO:3 DIO:4 DIO:5"), IOStandard("LVCMOS33"),
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Misc("SLEW=FAST")),
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Subsignal("b", Pins("DIO:6 CLKIO:0"), IOStandard("LVCMOS33"),
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Misc("SLEW=FAST"))
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)
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]
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extclk = [
|
||||
("extclk", 0, Pins("CLKIO:1"), IOStandard("LVCMOS33"))
|
||||
]
|
||||
|
||||
sevenseg = [
|
||||
("sevenseg", 0,
|
||||
Subsignal("segment7", Pins("GPIO:12"), IOStandard("LVTTL")), # A
|
||||
Subsignal("segment6", Pins("GPIO:13"), IOStandard("LVTTL")), # B
|
||||
Subsignal("segment5", Pins("GPIO:14"), IOStandard("LVTTL")), # C
|
||||
Subsignal("segment4", Pins("GPIO:15"), IOStandard("LVTTL")), # D
|
||||
Subsignal("segment3", Pins("GPIO:16"), IOStandard("LVTTL")), # E
|
||||
Subsignal("segment2", Pins("GPIO:17"), IOStandard("LVTTL")), # F
|
||||
Subsignal("segment1", Pins("GPIO:18"), IOStandard("LVTTL")), # G
|
||||
Subsignal("segment0", Pins("GPIO:19"), IOStandard("LVTTL")), # Dot
|
||||
Subsignal("enable0", Pins("GPIO:8"), IOStandard("LVTTL")), # EN0
|
||||
Subsignal("enable1", Pins("GPIO:9"), IOStandard("LVTTL")), # EN1
|
||||
Subsignal("enable2", Pins("GPIO:10"), IOStandard("LVTTL")), # EN2
|
||||
Subsignal("enable3", Pins("GPIO:11"), IOStandard("LVTTL")) # EN2
|
||||
)
|
||||
]
|
||||
|
||||
ps2 = [
|
||||
("ps2", 0,
|
||||
Subsignal("clk", Pins("LED:1"), IOStandard("LVCMOS33")),
|
||||
Subsignal("data", Pins("LED:0"), IOStandard("LVCMOS33"))
|
||||
)
|
||||
]
|
||||
|
||||
audio = [
|
||||
("audio", 0,
|
||||
Subsignal("l", Pins("GPIO:29"), IOStandard("LVTTL")),
|
||||
Subsignal("r", Pins("GPIO:28"), IOStandard("LVTTL"))
|
||||
)
|
||||
]
|
||||
|
||||
|
||||
class Platform(XilinxPlatform):
|
||||
default_clk_name = "clk50"
|
||||
default_clk_period = 20
|
||||
|
||||
def __init__(self, device="xc3s200a-4-vq100"):
|
||||
XilinxPlatform.__init__(self, device, _io, _connectors)
|
||||
# Small device- optimize for AREA instead of SPEED (LM32 runs at about
|
||||
# 60-65MHz in AREA configuration).
|
||||
self.toolchain.xst_opt = """-ifmt MIXED
|
||||
-use_new_parser yes
|
||||
-opt_mode AREA
|
||||
-register_balancing yes"""
|
||||
|
||||
def create_programmer(self):
|
||||
raise NotImplementedError
|
||||
|
|
@ -1,131 +0,0 @@
|
|||
from litex.build.generic_platform import *
|
||||
from litex.build.xilinx import XilinxPlatform
|
||||
|
||||
|
||||
_io = [
|
||||
("clk100", 0, Pins("V10"), IOStandard("LVCMOS33")),
|
||||
("clk12", 0, Pins("D9"), IOStandard("LVCMOS33")),
|
||||
|
||||
("serial", 0,
|
||||
Subsignal("tx", Pins("B8"), IOStandard("LVCMOS33"),
|
||||
Misc("SLEW=FAST")),
|
||||
Subsignal("rx", Pins("A8"), IOStandard("LVCMOS33"),
|
||||
Misc("SLEW=FAST"))),
|
||||
|
||||
("spiflash", 0,
|
||||
Subsignal("cs_n", Pins("V3")),
|
||||
Subsignal("clk", Pins("R15")),
|
||||
Subsignal("mosi", Pins("T13")),
|
||||
Subsignal("miso", Pins("R13"), Misc("PULLUP")),
|
||||
IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
|
||||
|
||||
("ddram_clock", 0,
|
||||
Subsignal("p", Pins("G3")),
|
||||
Subsignal("n", Pins("G1")),
|
||||
IOStandard("MOBILE_DDR")),
|
||||
|
||||
("ddram", 0,
|
||||
Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")),
|
||||
Subsignal("ba", Pins("F2 F1")),
|
||||
Subsignal("cke", Pins("H7")),
|
||||
Subsignal("ras_n", Pins("L5")),
|
||||
Subsignal("cas_n", Pins("K5")),
|
||||
Subsignal("we_n", Pins("E3")),
|
||||
Subsignal(
|
||||
"dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1")
|
||||
),
|
||||
Subsignal("dqs", Pins("L4 P2")),
|
||||
Subsignal("dm", Pins("K3 K4")),
|
||||
IOStandard("MOBILE_DDR")),
|
||||
|
||||
# Small DIP switches
|
||||
# DP1 (user_sw:0) -> DP8 (user_sw:7)
|
||||
("user_sw", 0, Pins("F17"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
("user_sw", 1, Pins("F18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
("user_sw", 2, Pins("E16"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
("user_sw", 3, Pins("E18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
("user_sw", 4, Pins("D18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
("user_sw", 5, Pins("D17"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
("user_sw", 6, Pins("C18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
("user_sw", 7, Pins("C17"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
|
||||
# Despite being marked as "sw" these are actually buttons which need
|
||||
# debouncing.
|
||||
# sw1 (user_btn:0) through sw6 (user_btn:5)
|
||||
("user_btn", 0, Pins("M18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
("user_btn", 1, Pins("L18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
("user_btn", 2, Pins("M16"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
("user_btn", 3, Pins("L17"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
("user_btn", 4, Pins("K17"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
# Use SW6 as the reset button for now.
|
||||
("user_btn", 5, Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
|
||||
|
||||
# LEDs 1 through 8
|
||||
("user_led", 0, Pins("P15"), IOStandard("LVCMOS33"), Drive(8)),
|
||||
("user_led", 1, Pins("P16"), IOStandard("LVCMOS33"), Drive(8)),
|
||||
("user_led", 2, Pins("N15"), IOStandard("LVCMOS33"), Drive(8)),
|
||||
("user_led", 3, Pins("N16"), IOStandard("LVCMOS33"), Drive(8)),
|
||||
("user_led", 4, Pins("U17"), IOStandard("LVCMOS33"), Drive(8)),
|
||||
("user_led", 5, Pins("U18"), IOStandard("LVCMOS33"), Drive(8)),
|
||||
("user_led", 6, Pins("T17"), IOStandard("LVCMOS33"), Drive(8)),
|
||||
("user_led", 7, Pins("T18"), IOStandard("LVCMOS33"), Drive(8)),
|
||||
|
||||
("mmc", 0,
|
||||
Subsignal("data", Pins("K14 G18 J13 L13"), IOStandard("LVCMOS33"),
|
||||
Misc("SLEW=FAST")),
|
||||
|
||||
Subsignal("cmd", Pins("G16"), IOStandard("LVCMOS33"),
|
||||
Misc("SLEW=FAST")),
|
||||
|
||||
Subsignal("clk", Pins("L12"), IOStandard("LVCMOS33"),
|
||||
Misc("SLEW=FAST"))),
|
||||
|
||||
("sevenseg", 0,
|
||||
Subsignal("segment7", Pins("A3"), IOStandard("LVCMOS33")), # A
|
||||
Subsignal("segment6", Pins("B4"), IOStandard("LVCMOS33")), # B
|
||||
Subsignal("segment5", Pins("A4"), IOStandard("LVCMOS33")), # C
|
||||
Subsignal("segment4", Pins("C4"), IOStandard("LVCMOS33")), # D
|
||||
Subsignal("segment3", Pins("C5"), IOStandard("LVCMOS33")), # E
|
||||
Subsignal("segment2", Pins("D6"), IOStandard("LVCMOS33")), # F
|
||||
Subsignal("segment1", Pins("C6"), IOStandard("LVCMOS33")), # G
|
||||
Subsignal("segment0", Pins("A5"), IOStandard("LVCMOS33")), # Dot
|
||||
Subsignal("enable0", Pins("B2"), IOStandard("LVCMOS33")), # EN0
|
||||
Subsignal("enable1", Pins("A2"), IOStandard("LVCMOS33")), # EN1
|
||||
Subsignal("enable2", Pins("B3"), IOStandard("LVCMOS33"))), # EN2
|
||||
|
||||
|
||||
("audio", 0,
|
||||
Subsignal("channel1", Pins("B16"), IOStandard("LVCMOS33"),
|
||||
Misc("SLEW=FAST")),
|
||||
Subsignal("channel2", Pins("A16"), IOStandard("LVCMOS33"),
|
||||
Misc("SLEW=FAST"))),
|
||||
|
||||
("vga_out", 0,
|
||||
Subsignal("hsync_n", Pins("B12"), IOStandard("LVCMOS33"),
|
||||
Misc("SLEW=FAST")),
|
||||
Subsignal("vsync_n", Pins("A12"), IOStandard("LVCMOS33"),
|
||||
Misc("SLEW=FAST")),
|
||||
Subsignal("r", Pins("A9 B9 C9"), IOStandard("LVCMOS33"),
|
||||
Misc("SLEW=FAST")),
|
||||
Subsignal("g", Pins("C10 A10 C11"), IOStandard("LVCMOS33"),
|
||||
Misc("SLEW=FAST")),
|
||||
Subsignal("b", Pins("B11 A11"), IOStandard("LVCMOS33"),
|
||||
Misc("SLEW=FAST")))
|
||||
]
|
||||
|
||||
_connectors = [
|
||||
("P6", "T3 R3 V5 U5 V4 T4 V7 U7"),
|
||||
("P7", "V11 U11 V13 U13 T10 R10 T11 R11"),
|
||||
("P8", "L16 L15 K16 K15 J18 J16 H18 H17")
|
||||
]
|
||||
|
||||
|
||||
class Platform(XilinxPlatform):
|
||||
default_clk_name = "clk100"
|
||||
default_clk_period = 10
|
||||
|
||||
def __init__(self):
|
||||
XilinxPlatform.__init__(self, "xc6slx9-csg324-2", _io, _connectors)
|
||||
|
||||
def create_programmer(self):
|
||||
raise NotImplementedError
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
from litex.build.generic_platform import *
|
||||
from litex.build.xilinx import XilinxPlatform
|
||||
from litex.build.xilinx.programmer import XC3SProg
|
||||
|
||||
|
||||
_io = [
|
||||
("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
|
||||
|
||||
("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")),
|
||||
|
||||
("serial", 0,
|
||||
Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
|
||||
Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP"))
|
||||
),
|
||||
|
||||
("spiflash", 0,
|
||||
Subsignal("cs_n", Pins("P38")),
|
||||
Subsignal("clk", Pins("P70")),
|
||||
Subsignal("mosi", Pins("P64")),
|
||||
Subsignal("miso", Pins("P65"), Misc("PULLUP")),
|
||||
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
|
||||
),
|
||||
("spiflash2x", 0,
|
||||
Subsignal("cs_n", Pins("P38")),
|
||||
Subsignal("clk", Pins("P70")),
|
||||
Subsignal("dq", Pins("P64", "P65")),
|
||||
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
|
||||
),
|
||||
|
||||
("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
|
||||
("sdram", 0,
|
||||
Subsignal("a", Pins("P140 P139 P138 P137 P46 P45 P44",
|
||||
"P43 P41 P40 P141 P35 P34")),
|
||||
Subsignal("ba", Pins("P143 P142")),
|
||||
Subsignal("cs_n", Pins("P1")),
|
||||
Subsignal("cke", Pins("P33")),
|
||||
Subsignal("ras_n", Pins("P2")),
|
||||
Subsignal("cas_n", Pins("P5")),
|
||||
Subsignal("we_n", Pins("P6")),
|
||||
Subsignal("dq", Pins("P9 P10 P11 P12 P14 P15 P16 P8 P21 P22 P23 P24 P26 P27 P29 P30")),
|
||||
Subsignal("dm", Pins("P7 P17")),
|
||||
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
|
||||
)
|
||||
]
|
||||
|
||||
_connectors = [
|
||||
("A", "P48 P51 P56 P58 P61 P66 P67 P75 P79 P81 P83 P85 P88 P93 P98 P100"),
|
||||
("B", "P99 P97 P92 P87 P84 P82 P80 P78 P74 P95 P62 P59 P57 P55 P50 P47"),
|
||||
("C", "P114 P115 P116 P117 P118 P119 P120 P121 P123 P124 P126 P127 P131 P132 P133 P134")
|
||||
]
|
||||
|
||||
|
||||
class Platform(XilinxPlatform):
|
||||
default_clk_name = "clk32"
|
||||
default_clk_period = 31.25
|
||||
|
||||
def __init__(self):
|
||||
XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors)
|
||||
|
||||
def create_programmer(self):
|
||||
return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit")
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
from litex.build.generic_platform import *
|
||||
from litex.build.lattice import LatticePlatform
|
||||
from litex.build.lattice.programmer import TinyFpgaBProgrammer
|
||||
|
||||
_io = [
|
||||
("usb", 0,
|
||||
Subsignal("d_p", Pins("A3")),
|
||||
Subsignal("d_n", Pins("A4")),
|
||||
IOStandard("LVCMOS33")
|
||||
),
|
||||
|
||||
("spiflash", 0,
|
||||
Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")),
|
||||
Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")),
|
||||
Subsignal("mosi", Pins("G6"), IOStandard("LVCMOS33")),
|
||||
Subsignal("miso", Pins("H7"), IOStandard("LVCMOS33"))
|
||||
),
|
||||
|
||||
("clk16", 0, Pins("B4"), IOStandard("LVCMOS33"))
|
||||
]
|
||||
|
||||
_connectors = [
|
||||
# B2-J1, Pins 4-13
|
||||
# D9-C9, Pins 18-19, Pins 21-24
|
||||
# E8, Pin 20 (Input only)
|
||||
("GPIO", "B2 A2 A1 B1 C1 D1 E1 G1 H1 J1 D9 C9 A9 A8 A7 A6"),
|
||||
("GBIN", "E8")
|
||||
]
|
||||
|
||||
|
||||
# Default peripherals
|
||||
serial = [
|
||||
("serial", 0,
|
||||
Subsignal("tx", Pins("GPIO:0")),
|
||||
Subsignal("rx", Pins("GPIO:1")),
|
||||
IOStandard("LVCMOS33")
|
||||
)
|
||||
]
|
||||
|
||||
|
||||
class Platform(LatticePlatform):
|
||||
default_clk_name = "clk16"
|
||||
default_clk_period = 62.5
|
||||
|
||||
def __init__(self):
|
||||
LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors,
|
||||
toolchain="icestorm")
|
||||
|
||||
def create_programmer(self):
|
||||
return TinyFpgaBProgrammer()
|
||||
|
|
@ -71,20 +71,14 @@ class TestTargets(unittest.TestCase):
|
|||
def test_simple(self):
|
||||
platforms = [
|
||||
"arty",
|
||||
"arty_s7",
|
||||
"de0nano",
|
||||
"genesys2",
|
||||
"icestick",
|
||||
"kc705",
|
||||
"kcu105",
|
||||
"machxo3",
|
||||
"mercury",
|
||||
"mimasv2",
|
||||
"minispartan6",
|
||||
"nexys4ddr",
|
||||
"nexys_video",
|
||||
"papilio_pro",
|
||||
"tinyfpga_b",
|
||||
"tinyfpga_bx",
|
||||
"versa_ecp3",
|
||||
"versa_ecp5"
|
||||
|
|
|
|||
Loading…
Reference in New Issue