litesata: cleanup README/doc
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@ -91,34 +91,38 @@ devel [AT] lists.m-labs.hk.
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python3 setup.py install
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cd ..
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3. Obtain MiSoC:
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3. Obtain MiSoC and install it:
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git clone https://github.com/m-labs/misoc --recursive
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cd misoc
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python3 setup.pu install
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cd ..
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5. Build and load BIST design (only for KC705 for now):
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go to misoclib/mem/litesata/example_designs/
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run ./make.py all load-bitstream
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go to ./example_designs/
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run ./make.py all
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6. Test design (only for KC705 for now):
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go to [..]/example_designs/test/
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run ./bist.py --port your_serial_port
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go to ./example_designs/test/
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run ./bist.py --port <your_serial_port>
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7. If you only want to build the core and use it with your
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regular design flow:
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go to misoclib/mem/litesata/example_designs/
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go to ./litesata/example_designs/
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run ./make.py -t core build-core
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You can customize the core in [..]/example_design/targets/core.py
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You can customize the core in ./example_designs/targets/core.py
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[> Simulations:
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Simulations are available in ./lib/sata/test:
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Simulations are available in ./test:
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- crc_tb
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- scrambler_tb
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- phy_datapath_tb
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- link_tb
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- command_tb
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- bist_tb
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hdd.py is a simplified HDD model implementing all SATA layers.
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To run a simulation, move to ./lib/sata/test and run:
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make simulation_name
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Models for all the layers of SATA and a simplified HDD model are
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provided.
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To run a simulation, go to ./test and run:
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make <simulation_name>
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[> Tests :
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A synthetizable BIST is provided and can be controlled with ./test/bist.py
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@ -15,6 +15,6 @@ Simulations are available in ./lib/sata/test:
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- command_tb
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- bist_tb
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hdd.py is a simplified HDD model implementing all SATA layers.
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To run a simulation, move to ./lib/sata/test and run:
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- make simulation_name
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Models for all the layers of SATA and a simplified HDD model are provided.
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To run a simulation, go to ./test and run:
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- make <simulation_name>
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