build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input.
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@ -275,11 +275,28 @@ class XilinxDDRInputS7:
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def lower(dr):
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return XilinxDDRInputImplS7(dr.i, dr.o1, dr.o2, dr.clk)
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# 7-Series SDROutput -------------------------------------------------------------------------------
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class XilinxSDROutputS7:
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@staticmethod
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def lower(dr):
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return XilinxDDROutputImplS7(dr.i, dr.i, dr.o, dr.clk)
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# 7-Series SDRInput --------------------------------------------------------------------------------
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class XilinxSDRInputS7:
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@staticmethod
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def lower(dr):
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return XilinxDDRInputImplS7(dr.i, dr.o, Signal(), dr.clk)
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# 7-Series Special Overrides -----------------------------------------------------------------------
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xilinx_s7_special_overrides = {
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DDROutput: XilinxDDROutputS7,
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DDRInput: XilinxDDRInputS7
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DDRInput: XilinxDDRInputS7,
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SDROutput: XilinxSDROutputS7,
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SDRInput: XilinxSDRInputS7,
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}
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# Ultrascale DDROutput -----------------------------------------------------------------------------
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@ -322,11 +339,28 @@ class XilinxDDRInputUS:
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def lower(dr):
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return XilinxDDRInputImplUS(dr.i, dr.o1, dr.o2, dr.clk)
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# Ultrascale SDROutput -----------------------------------------------------------------------------
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class XilinxSDROutputUS:
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@staticmethod
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def lower(dr):
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return XilinxDDROutputImplUS(dr.i, dr.i, dr.o, dr.clk)
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# Ultrascale SDRInput ------------------------------------------------------------------------------
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class XilinxSDRInputUS:
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@staticmethod
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def lower(dr):
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return XilinxDDRInputImplUS(dr.i, dr.o, Signal(), dr.clk)
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# Ultrascale Specials Overrides --------------------------------------------------------------------
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xilinx_us_special_overrides = {
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DDROutput: XilinxDDROutputUS,
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DDRInput: XilinxDDRInputUS
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DDRInput: XilinxDDRInputUS,
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SDROutput: XilinxSDROutputUS,
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SDRInput: XilinxSDRInputUS,
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}
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# Yosys Run ----------------------------------------------------------------------------------------
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