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soc/integration: add initial JTAG-UART support to UARTbone.

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This commit is contained in:
Florent Kermarrec 2021-01-22 14:17:44 +01:00
parent e8cfe3b6ea
commit 697ff7447c
2 changed files with 14 additions and 6 deletions
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11
litex/soc/cores/uart.py
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@ -378,12 +378,12 @@ class Stream2Wishbone(Module):
class UARTBone(Stream2Wishbone): class UARTBone(Stream2Wishbone):
def __init__(self, pads, clk_freq, baudrate=115200, cd="sys"): def __init__(self, phy, clk_freq, cd="sys"):
if cd == "sys": if cd == "sys":
self.submodules.phy = RS232PHY(pads, clk_freq, baudrate) self.submodules.phy = phy
Stream2Wishbone.__init__(self, self.phy, clk_freq=clk_freq) Stream2Wishbone.__init__(self, self.phy, clk_freq=clk_freq)
else: else:
self.submodules.phy = ClockDomainsRenamer(cd)(RS232PHY(pads, clk_freq, baudrate)) self.submodules.phy = ClockDomainsRenamer(cd)(phy)
self.submodules.tx_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=cd) self.submodules.tx_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=cd)
self.submodules.rx_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from=cd, cd_to="sys") self.submodules.rx_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from=cd, cd_to="sys")
self.comb += self.phy.source.connect(self.rx_cdc.sink) self.comb += self.phy.source.connect(self.rx_cdc.sink)
@ -392,7 +392,10 @@ class UARTBone(Stream2Wishbone):
self.comb += self.rx_cdc.source.connect(self.sink) self.comb += self.rx_cdc.source.connect(self.sink)
self.comb += self.source.connect(self.tx_cdc.sink) self.comb += self.source.connect(self.tx_cdc.sink)
class UARTWishboneBridge(UARTBone): pass class UARTWishboneBridge(UARTBone):
def __init__(self, pads, clk_freq, baudrate=115200, cd="sys"):
self.submodules.phy = RS232PHY(pads, clk_freq, baudrate)
UARTBone.__init__(self, self.phy, clk_freq, cd)
# UART Multiplexer --------------------------------------------------------------------------------- # UART Multiplexer ---------------------------------------------------------------------------------

9
litex/soc/integration/soc.py
View file

@ -1163,10 +1163,15 @@ class LiteXSoC(SoC):
# Add UARTbone --------------------------------------------------------------------------------- # Add UARTbone ---------------------------------------------------------------------------------
def add_uartbone(self, name="serial", clk_freq=None, baudrate=115200, cd="sys"): def add_uartbone(self, name="serial", clk_freq=None, baudrate=115200, cd="sys"):
from litex.soc.cores import uart from litex.soc.cores import uart
if name == "jtag_uart":
from litex.soc.cores.jtag import JTAGPHY
phy = JTAGPHY(device=self.platform.device)
else:
phy = uart.UARTPHY(platform.request(name), clk_freq, bandrate)
self.submodules += phy
self.submodules.uartbone = uart.UARTBone( self.submodules.uartbone = uart.UARTBone(
pads = self.platform.request(name), phy = phy,
clk_freq = clk_freq if clk_freq is not None else self.sys_clk_freq, clk_freq = clk_freq if clk_freq is not None else self.sys_clk_freq,
baudrate = baudrate,
cd = cd) cd = cd)
self.bus.add_master(name="uartbone", master=self.uartbone.wishbone) self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)